<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/pci/dwc, branch linux-4.13.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.13.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.13.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2017-07-04T16:00:57Z</updated>
<entry>
<title>Merge branch 'pci/host-qcom' into next</title>
<updated>2017-07-04T16:00:57Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-07-04T16:00:57Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bec36cfa7bd43a1e4484b14ff6144855f3446c4c'/>
<id>urn:sha1:bec36cfa7bd43a1e4484b14ff6144855f3446c4c</id>
<content type='text'>
* pci/host-qcom:
  PCI: qcom: Limit TLP size to 2K to work around hardware issue
  PCI: qcom: Fix spelling mistake: "asser" -&gt; "assert"
  PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc
  PCI: qcom: Add support for IPQ4019 PCIe controller
</content>
</entry>
<entry>
<title>Merge branch 'pci/host-kirin' into next</title>
<updated>2017-07-04T16:00:56Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-07-04T16:00:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8a08e7eada357e853ff448482208a5ee7b94201a'/>
<id>urn:sha1:8a08e7eada357e853ff448482208a5ee7b94201a</id>
<content type='text'>
* pci/host-kirin:
  PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driver
</content>
</entry>
<entry>
<title>Merge branch 'pci/host-imx6' into next</title>
<updated>2017-07-03T13:00:32Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-07-03T13:00:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=beaba77cf23f1734fc06ea90932526567c95ac25'/>
<id>urn:sha1:beaba77cf23f1734fc06ea90932526567c95ac25</id>
<content type='text'>
* pci/host-imx6:
  PCI: imx6: Add regulator support
</content>
</entry>
<entry>
<title>Merge branch 'pci/host-dra7xx' into next</title>
<updated>2017-07-03T13:00:30Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-07-03T13:00:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ecf75c46e6a43eb083c9dfbbe7903ec81dcd524a'/>
<id>urn:sha1:ecf75c46e6a43eb083c9dfbbe7903ec81dcd524a</id>
<content type='text'>
* pci/host-dra7xx:
  PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN
  PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
</content>
</entry>
<entry>
<title>Merge branch 'pci/host-designware' into next</title>
<updated>2017-07-03T13:00:30Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-07-03T13:00:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f011a5f8bacbf62f9de16c2a4c7e73dcabfae383'/>
<id>urn:sha1:f011a5f8bacbf62f9de16c2a4c7e73dcabfae383</id>
<content type='text'>
* pci/host-designware:
  PCI: dwc: Constify dw_pcie_host_ops structures
  PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD
</content>
</entry>
<entry>
<title>Merge branch 'pci/irq-fixups' into next</title>
<updated>2017-07-03T13:00:29Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-07-03T13:00:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=44d745fb5d06cce62501a39e9dd47a47b111777b'/>
<id>urn:sha1:44d745fb5d06cce62501a39e9dd47a47b111777b</id>
<content type='text'>
* pci/irq-fixups:
  arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()
  PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions
  PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions
  PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions
  PCI: altera: Drop pci_fixup_irqs()
  PCI: versatile: Drop pci_fixup_irqs()
  PCI: generic: Drop pci_fixup_irqs()
  PCI: faraday: Drop pci_fixup_irqs()
  PCI: designware: Drop pci_fixup_irqs()
  PCI: iproc: Drop pci_fixup_irqs()
  PCI: rcar: Drop pci_fixup_irqs()
  PCI: xilinx: Drop pci_fixup_irqs()
  PCI: tegra: Drop pci_fixup_irqs()
  ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers
  PCI: Add a call to pci_assign_irq() in pci_device_probe()
  OF/PCI: Update of_irq_parse_and_map_pci() comment
  PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it
  PCI: Add IRQ mapping function pointers to pci_host_bridge struct
  PCI: Build setup-irq.o on all arches
  PCI: Remove pci_scan_root_bus_msi()
  PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()
  ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: Make pci_register_host_bridge() PCI core internal
  PCI: Add pci_scan_root_bus_bridge() interface
  PCI: tegra: Fix host bridge memory leakage
  PCI: faraday: Fix host bridge memory leakage
  PCI: Add devm_pci_alloc_host_bridge() interface
  PCI: Add pci_free_host_bridge() interface
  PCI: Initialize bridge release function at bridge allocation
  PCI: faraday: Convert IRQ masking to raw PCI config accessors
  PCI: iproc: Convert link check to raw PCI config accessors
  PCI: xilinx-nwl: Remove nwl_pcie_enable_msi() unused bus parameter
</content>
</entry>
<entry>
<title>PCI: qcom: Limit TLP size to 2K to work around hardware issue</title>
<updated>2017-07-02T23:45:09Z</updated>
<author>
<name>Srinivas Kandagatla</name>
</author>
<published>2017-06-29T15:34:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b8f2a856560361753a6ac846977e4c1e21bf64f7'/>
<id>urn:sha1:b8f2a856560361753a6ac846977e4c1e21bf64f7</id>
<content type='text'>
Limit TLP size to 2K to work around a hardware bug in the v0 version of
PCIe IP.  When using default TLP size of 4K, the internal buffer gets
corrupted due to this hardware bug.

This bug was originally noticed during ssh session between APQ8064-based
board and PC.  Network packets got corrupted randomly and terminated the ssh
session due to this bug.

Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: qcom: Fix spelling mistake: "asser" -&gt; "assert"</title>
<updated>2017-07-02T23:45:09Z</updated>
<author>
<name>Colin Ian King</name>
</author>
<published>2017-05-31T05:34:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7a5966eb9123d9e335c0ea04f0fbb0c71e418186'/>
<id>urn:sha1:7a5966eb9123d9e335c0ea04f0fbb0c71e418186</id>
<content type='text'>
Trivial fix to spelling mistake in dev_err message.

Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc</title>
<updated>2017-07-02T23:45:08Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-05-24T20:19:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5d0f1b84c5265f129029885e768a2f451f48bcc2'/>
<id>urn:sha1:5d0f1b84c5265f129029885e768a2f451f48bcc2</id>
<content type='text'>
Previously the v0, v1, and v2 functions were not grouped together in a
consistent order.  Reorder them to make them consistent.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: qcom: Add support for IPQ4019 PCIe controller</title>
<updated>2017-07-02T23:45:08Z</updated>
<author>
<name>John Crispin</name>
</author>
<published>2017-05-23T20:02:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=90d52d57ccace5cd590ae642765b510240986546'/>
<id>urn:sha1:90d52d57ccace5cd590ae642765b510240986546</id>
<content type='text'>
Add support for the IPQ4019 PCIe controller.  IPQ4019 supports Gen 1/2, one
lane, one PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.

The core init is the same as for the MSM8996, however the clocks and reset
lines differ.

[bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile
issues]
Signed-off-by: John Crispin &lt;john@phrozen.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Stanimir Varbanov &lt;svarbanov@mm-sol.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;		# binding</content>
</entry>
</feed>
