<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/pci/dmar.c, branch linux-2.6.31.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.31.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.31.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2009-10-22T22:11:51Z</updated>
<entry>
<title>intel-iommu: Cope with broken HP DC7900 BIOS</title>
<updated>2009-10-22T22:11:51Z</updated>
<author>
<name>David Woodhouse</name>
</author>
<published>2009-08-04T08:17:20Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=af0ce40996ee98e12357f2a4775d6a65a7f54734'/>
<id>urn:sha1:af0ce40996ee98e12357f2a4775d6a65a7f54734</id>
<content type='text'>
commit 0815565adfe3f4c369110c57d8ffe83caefeed68 upstream.

Yet another reason why trusting this stuff to the BIOS was a bad idea.
The HP DC7900 BIOS reports an iommu at an address which just returns all
ones, when VT-d is disabled in the BIOS.

Fix up the missing iounmap in the error paths while we're at it.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
Cc: Arto Jantunen &lt;viiru@debian.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>VT-d: add device IOTLB invalidation support</title>
<updated>2009-05-18T13:45:13Z</updated>
<author>
<name>Yu Zhao</name>
</author>
<published>2009-05-18T05:51:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6ba6c3a4cacfd68bf970e3e04e2ff0d66fa0f695'/>
<id>urn:sha1:6ba6c3a4cacfd68bf970e3e04e2ff0d66fa0f695</id>
<content type='text'>
Support device IOTLB invalidation to flush the translation cached
in the Endpoint.

Signed-off-by: Yu Zhao &lt;yu.zhao@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>VT-d: parse ATSR in DMA Remapping Reporting Structure</title>
<updated>2009-05-18T13:45:09Z</updated>
<author>
<name>Yu Zhao</name>
</author>
<published>2009-05-18T05:51:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=aa5d2b515b6fca5f8a56eac84f7fa0a68c1ce9b7'/>
<id>urn:sha1:aa5d2b515b6fca5f8a56eac84f7fa0a68c1ce9b7</id>
<content type='text'>
Parse the Root Port ATS Capability Reporting Structure in the DMA
Remapping Reporting Structure ACPI table.

Signed-off-by: Yu Zhao &lt;yu.zhao@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: dmar_set_interrupt return error value</title>
<updated>2009-05-14T15:07:37Z</updated>
<author>
<name>Chris Wright</name>
</author>
<published>2009-05-13T22:55:52Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=dd7264355a203c3456dbba04db471947d3b55e7e'/>
<id>urn:sha1:dd7264355a203c3456dbba04db471947d3b55e7e</id>
<content type='text'>
dmar_set_interrupt feigns success when arch_setup_dmar_msi
fails, return error value.

Signed-off-by: Chris Wright &lt;chrisw@sous-sol.org&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: Tidy up iommu-&gt;gcmd handling</title>
<updated>2009-05-10T19:32:37Z</updated>
<author>
<name>David Woodhouse</name>
</author>
<published>2009-05-10T19:30:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c416daa98a584596df21ee2c26fac6579ee58f57'/>
<id>urn:sha1:c416daa98a584596df21ee2c26fac6579ee58f57</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing.</title>
<updated>2009-05-10T18:58:49Z</updated>
<author>
<name>David Woodhouse</name>
</author>
<published>2009-05-10T18:58:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1f0ef2aa18802a8ce7eb5a5164aaaf4d59073801'/>
<id>urn:sha1:1f0ef2aa18802a8ce7eb5a5164aaaf4d59073801</id>
<content type='text'>
As we just did for context cache flushing, clean up the logic around
whether we need to flush the iotlb or just the write-buffer, depending
on caching mode.

Fix the same bug in qi_flush_iotlb() that qi_flush_context() had -- it
isn't supposed to be returning an error; it's supposed to be returning a
flag which triggers a write-buffer flush.

Remove some superfluous conditional write-buffer flushes which could
never have happened because they weren't for non-present-to-present
mapping changes anyway.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: Clean up handling of "caching mode" vs. context flushing.</title>
<updated>2009-05-10T18:49:52Z</updated>
<author>
<name>David Woodhouse</name>
</author>
<published>2009-05-10T16:16:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4c25a2c1b90bf785fc2e2f0f0c74a80b3e070d39'/>
<id>urn:sha1:4c25a2c1b90bf785fc2e2f0f0c74a80b3e070d39</id>
<content type='text'>
It really doesn't make a lot of sense to have some of the logic to
handle caching vs. non-caching mode duplicated in qi_flush_context() and
__iommu_flush_context(), while the return value indicates whether the
caller should take other action which depends on the same thing.

Especially since qi_flush_context() thought it was returning something
entirely different anyway.

This patch makes qi_flush_context() and __iommu_flush_context() both
return void, removes the 'non_present_entry_flush' argument and makes
the only call site which _set_ that argument to 1 do the right thing.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>Intel IOMMU Pass Through Support</title>
<updated>2009-04-29T05:54:34Z</updated>
<author>
<name>Fenghua Yu</name>
</author>
<published>2009-04-25T00:30:20Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4ed0d3e6c64cfd9ba4ceb2099b10d1cf8ece4320'/>
<id>urn:sha1:4ed0d3e6c64cfd9ba4ceb2099b10d1cf8ece4320</id>
<content type='text'>
The patch adds kernel parameter intel_iommu=pt to set up pass through
mode in context mapping entry. This disables DMAR in linux kernel; but
KVM still runs on VT-d and interrupt remapping still works.

In this mode, kernel uses swiotlb for DMA API functions but other VT-d
functionalities are enabled for KVM. KVM always uses multi level
translation page table in VT-d. By default, pass though mode is disabled
in kernel.

This is useful when people don't want to enable VT-d DMAR in kernel but
still want to use KVM and interrupt remapping for reasons like DMAR
performance concern or debug purpose.

Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Acked-by: Weidong Han &lt;weidong@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: Avoid panic() for DRHD at address zero.</title>
<updated>2009-04-11T05:27:48Z</updated>
<author>
<name>David Woodhouse</name>
</author>
<published>2009-04-11T05:27:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e523b38e2f568af58baa13120a994cbf24e6dee0'/>
<id>urn:sha1:e523b38e2f568af58baa13120a994cbf24e6dee0</id>
<content type='text'>
If the BIOS does something obviously stupid, like claiming that the
registers for the IOMMU are at physical address zero, then print a nasty
message and abort, rather than trying to set up the IOMMU and then later
panicking.

It's becoming more and more obvious that trusting this stuff to the BIOS
was a mistake.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-iommu: Handle PCI domains appropriately.</title>
<updated>2009-04-04T09:43:31Z</updated>
<author>
<name>David Woodhouse</name>
</author>
<published>2009-04-04T00:45:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=276dbf997043cbf38f0087624e0f9c51742c8885'/>
<id>urn:sha1:276dbf997043cbf38f0087624e0f9c51742c8885</id>
<content type='text'>
We were comparing {bus,devfn} and assuming that a match meant it was the
same device. It doesn't -- the same {bus,devfn} can exist in
multiple PCI domains. Include domain number in device identification
(and call it 'segment' in most places, because there's already a lot of
references to 'domain' which means something else, and this code is
infected with ACPI thinking already).

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
</entry>
</feed>
