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<title>kernel.git/drivers/pci/controller/dwc/Kconfig, branch linux-5.4.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.4.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.4.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2019-09-23T21:10:28Z</updated>
<entry>
<title>Merge branch 'lorenzo/pci/tegra'</title>
<updated>2019-09-23T21:10:28Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2019-09-23T21:10:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3efa7f1febe60531c0b5f0397c3e87cfa48591f7'/>
<id>urn:sha1:3efa7f1febe60531c0b5f0397c3e87cfa48591f7</id>
<content type='text'>
  - Fix Tegra OF node reference leak (Nishka Dasgupta)

  - Add #defines for PCIe Data Link Feature and Physical Layer 16.0 GT/s
    features (Vidya Sagar)

  - Disable MSI for Tegra Root Ports since they don't support using MSI for
    all Root Port events (Vidya Sagar)

  - Group DesignWare write-protected register writes together (Vidya Sagar)

  - Move DesignWare capability search interfaces so they can be used by
    both host and endpoint drivers (Vidya Sagar)

  - Add DesignWare extended capability search interfaces (Vidya Sagar)

  - Export dw_pcie_wait_for_link() so drivers can be modules (Vidya Sagar)

  - Add "snps,enable-cdm-check" DT binding for Configuration Dependent
    Module (CDM) register checking (Vidya Sagar)

  - Add DesignWare support for "snps,enable-cdm-check" CDM checking (Vidya
    Sagar)

  - Add "supports-clkreq" DT binding for host drivers to decide whether to
    advertise low power features (Vidya Sagar)

  - Add DT binding for Tegra194 (Vidya Sagar)

  - Add DT binding for Tegra194 P2U (PIPE to UPHY) block (Vidya Sagar)

  - Add support for Tegra194 P2U (PIPE to UPHY) (Vidya Sagar)

  - Add support for Tegra194 host controller (Vidya Sagar)

  - Add Tegra support for sideband PERST# and CLKREQ# for C5 (Vidya Sagar)

  - Add Tegra support for slot regulators for p2972-0000 platform (Vidya
    Sagar)

* lorenzo/pci/tegra:
  arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
  arm64: tegra: Add configuration for PCIe C5 sideband signals
  PCI: tegra: Add support to enable slot regulators
  PCI: tegra: Add support to configure sideband pins
  dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
  dt-bindings: PCI: tegra: Add sideband pins configuration entries
  PCI: tegra: Add Tegra194 PCIe support
  phy: tegra: Add PCIe PIPE2UPHY support
  dt-bindings: PHY: P2U: Add Tegra194 P2U block
  dt-bindings: PCI: tegra: Add device tree support for Tegra194
  dt-bindings: Add PCIe supports-clkreq property
  PCI: dwc: Add support to enable CDM register check
  dt-bindings: PCI: designware: Add binding for CDM register check
  PCI: dwc: Export dw_pcie_wait_for_link() API
  PCI: dwc: Add extended configuration space capability search API
  PCI: dwc: Move config space capability search API
  PCI: dwc: Group DBI registers writes requiring unlocking
  PCI: Disable MSI for Tegra root ports
  PCI: Add #defines for some of PCIe spec r4.0 features
  PCI: tegra: Fix OF node reference leak
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/layerscape'</title>
<updated>2019-09-23T21:10:23Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2019-09-23T21:10:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5adc7d510627fa940cde9beafba49c889c5656a7'/>
<id>urn:sha1:5adc7d510627fa940cde9beafba49c889c5656a7</id>
<content type='text'>
  - Mark Layerscape endpoint BARs 2 and 4 as 64-bit (Xiaowei Bao)

  - Add CONFIG_PCI_LAYERSCAPE_EP so EP/RC can be built separately (Xiaowei
    Bao)

* remotes/lorenzo/pci/layerscape:
  PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
  PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driver
</content>
</entry>
<entry>
<title>PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver</title>
<updated>2019-09-16T13:16:44Z</updated>
<author>
<name>Jonathan Chocron</name>
</author>
<published>2019-09-12T13:02:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a8daea94754989f6c48dafda840482cbc9f882f9'/>
<id>urn:sha1:a8daea94754989f6c48dafda840482cbc9f882f9</id>
<content type='text'>
This driver is DT based and utilizes the DesignWare APIs.

It allows using a smaller ECAM range for a larger bus range -
usually an entire bus uses 1MB of address space, but the driver
can use it for a larger number of buses. This is achieved by using a HW
mechanism which allows changing the BUS part of the "final" outgoing
config transaction. There are 2 HW regs, one which is basically a
bitmask determining which bits to take from the AXI transaction itself
and another which holds the complementary part programmed by the
driver.

All link initializations are handled by the boot FW.

Signed-off-by: Jonathan Chocron &lt;jonnyc@amazon.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Gustavo Pimentel &lt;gustavo.pimentel@synopsys.com&gt;
Reviewed-by: Andrew Murray &lt;andrew.murray@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: tegra: Add Tegra194 PCIe support</title>
<updated>2019-09-08T12:00:53Z</updated>
<author>
<name>Vidya Sagar</name>
</author>
<published>2019-08-13T11:36:27Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=56e15a238d92788a2d09e0c5c26a5de1b3156931'/>
<id>urn:sha1:56e15a238d92788a2d09e0c5c26a5de1b3156931</id>
<content type='text'>
Add support for Synopsys DesignWare core IP based PCIe host controller
present in the Tegra194 SoC.

Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately</title>
<updated>2019-08-14T09:54:13Z</updated>
<author>
<name>Xiaowei Bao</name>
</author>
<published>2019-08-14T02:03:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b5b24617987f522abb5c42851ae505557f2c84f8'/>
<id>urn:sha1:b5b24617987f522abb5c42851ae505557f2c84f8</id>
<content type='text'>
Add CONFIG_PCI_LAYERSCAPE_EP so that endpoint and host controller
drivers can be built separately.

Signed-off-by: Xiaowei Bao &lt;xiaowei.bao@nxp.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: imx6: Simplify Kconfig depends on</title>
<updated>2019-07-05T15:44:41Z</updated>
<author>
<name>Leonard Crestez</name>
</author>
<published>2019-03-11T18:59:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7e8ab1b268b1ab2d2956823f93c7f3c62b9c2b26'/>
<id>urn:sha1:7e8ab1b268b1ab2d2956823f93c7f3c62b9c2b26</id>
<content type='text'>
The imx6 driver can be used on imx6sx without enabling support for
imx6q or imx7d but the "depends on" condition doesn't allow that.

Instead of making the condition even longer just make it depend on
"ARCH_MXC || COMPILE_TEST" instead.

Signed-off-by: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>PCI: keystone: Add support for PCIe EP in AM654x Platforms</title>
<updated>2019-05-01T14:50:13Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
</author>
<published>2019-03-25T09:39:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=23284ad677a94f26afc92017d540ccaf26c1a581'/>
<id>urn:sha1:23284ad677a94f26afc92017d540ccaf26c1a581</id>
<content type='text'>
Add PCIe EP support for AM654x Platforms in pci-keystone.c

Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
[lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: keystone: Add support for PCIe RC in AM654x Platforms</title>
<updated>2019-04-15T12:24:02Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
</author>
<published>2019-03-25T09:39:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=18b0415bc802a8bab5dedba5ae2757e83259e6ee'/>
<id>urn:sha1:18b0415bc802a8bab5dedba5ae2757e83259e6ee</id>
<content type='text'>
Add PCIe RC support for AM654x Platforms in pci-keystone.c

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: imx6: Add support for i.MX8MQ</title>
<updated>2019-02-04T12:04:53Z</updated>
<author>
<name>Andrey Smirnov</name>
</author>
<published>2019-02-02T00:15:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2d8ed461dbc9bc734185db92d2b9d1bb7b586b30'/>
<id>urn:sha1:2d8ed461dbc9bc734185db92d2b9d1bb7b586b30</id>
<content type='text'>
Add code needed to support i.MX8MQ variant.

Signed-off-by: Andrey Smirnov &lt;andrew.smirnov@gmail.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Chris Healy &lt;cphealy@gmail.com&gt;
Cc: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Cc: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Cc: "A.s. Dong" &lt;aisheng.dong@nxp.com&gt;
Cc: Richard Zhu &lt;hongxing.zhu@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/uniphier'</title>
<updated>2019-01-02T21:31:15Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2019-01-02T21:31:15Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cdf4f4dc118bafd97d0148d53730e396ece11afa'/>
<id>urn:sha1:cdf4f4dc118bafd97d0148d53730e396ece11afa</id>
<content type='text'>
  - Add UniPhier PCIe controller driver and DT bindings (Kunihiko Hayashi)

* remotes/lorenzo/pci/uniphier:
  PCI: uniphier: Add UniPhier PCIe host controller support
  dt-bindings: PCI: Add UniPhier PCIe host controller description

# Conflicts:
#	drivers/pci/controller/dwc/Kconfig
#	drivers/pci/controller/dwc/Makefile
</content>
</entry>
</feed>
