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<title>kernel.git/drivers/pci/ats.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.1.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.1.y'/>
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<updated>2019-02-26T10:08:07Z</updated>
<entry>
<title>PCI/ATS: Add pci_ats_page_aligned() interface</title>
<updated>2019-02-26T10:08:07Z</updated>
<author>
<name>Kuppuswamy Sathyanarayanan</name>
</author>
<published>2019-02-19T19:06:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8c938ddc6df3bbe72809db1be6c9f3af83f5d7a9'/>
<id>urn:sha1:8c938ddc6df3bbe72809db1be6c9f3af83f5d7a9</id>
<content type='text'>
Return the Page Aligned Request bit in the ATS Capability Register.

As per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit is
set, it indicates the Untranslated Addresses generated by the device are
always aligned to a 4096 byte boundary.

An IOMMU that can only translate page-aligned addresses can only be used
with devices that always produce aligned Untranslated Addresses. This
interface will be used by drivers for such IOMMUs to determine whether
devices can use the ATS service.

Cc: Ashok Raj &lt;ashok.raj@intel.com&gt;
Cc: Jacob Pan &lt;jacob.jun.pan@linux.intel.com&gt;
Cc: Keith Busch &lt;keith.busch@intel.com&gt;
Suggested-by: Ashok Raj &lt;ashok.raj@intel.com&gt;
Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>PCI/ATS: Add pci_prg_resp_pasid_required() interface.</title>
<updated>2019-02-26T10:07:05Z</updated>
<author>
<name>Kuppuswamy Sathyanarayanan</name>
</author>
<published>2019-02-19T19:04:51Z</published>
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<id>urn:sha1:e5567f5f67621877726f99be040af9fbedda37dc</id>
<content type='text'>
Return the PRG Response PASID Required bit in the Page Request
Status Register.

As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set, the device
expects a PASID TLP Prefix on PRG Response Messages when the
corresponding Page Requests had a PASID TLP Prefix. If Clear, the device
does not expect PASID TLP Prefixes on any PRG Response Message, and the
device behavior is undefined if the device receives a PRG Response Message
with a PASID TLP Prefix. Also the device behavior is undefined if this
bit is Set and the device receives a PRG Response Message with no PASID TLP
Prefix when the corresponding Page Requests had a PASID TLP Prefix.

This function will be used by drivers like IOMMU, if it is required to
check the status of the PRG Response PASID Required bit before enabling
the PASID support of the device.

Cc: Ashok Raj &lt;ashok.raj@intel.com&gt;
Cc: Jacob Pan &lt;jacob.jun.pan@linux.intel.com&gt;
Cc: Keith Busch &lt;keith.busch@intel.com&gt;
Suggested-by: Ashok Raj &lt;ashok.raj@intel.com&gt;
Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>PCI: Enable PASID only if entire path supports End-End TLP prefixes</title>
<updated>2018-06-30T19:10:03Z</updated>
<author>
<name>Sinan Kaya</name>
</author>
<published>2018-06-30T15:24:24Z</published>
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<id>urn:sha1:7ce3f912ae0a79e5d738a3ae1f158b281973e849</id>
<content type='text'>
A PCIe endpoint carries the process address space identifier (PASID) in
the TLP prefix as part of the memory read/write transaction. The address
information in the TLP is relevant only for a given PASID context.

An IOMMU takes PASID value and the address information from the
TLP to look up the physical address in the system.

PASID is an End-End TLP Prefix (PCIe r4.0, sec 6.20).  Sec 2.2.10.2 says

  It is an error to receive a TLP with an End-End TLP Prefix by a
  Receiver that does not support End-End TLP Prefixes. A TLP in
  violation of this rule is handled as a Malformed TLP. This is a
  reported error associated with the Receiving Port (see Section 6.2).

Prevent error condition by proactively requiring End-End TLP prefix to be
supported on the entire data path between the endpoint and the root port
before enabling PASID.

Signed-off-by: Sinan Kaya &lt;okaya@codeaurora.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Add "pci=noats" boot parameter</title>
<updated>2018-05-10T22:56:02Z</updated>
<author>
<name>Gil Kupfer</name>
</author>
<published>2018-05-10T22:56:02Z</published>
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<id>urn:sha1:cef74409ea79b0a37af6889e7abf7a2a9c47979b</id>
<content type='text'>
Adds a "pci=noats" boot parameter.  When supplied, all ATS related
functions fail immediately and the IOMMU is configured to not use
device-IOTLB.

Any function that checks for ATS capabilities directly against the devices
should also check this flag.  Currently, such functions exist only in IOMMU
drivers, and they are covered by this patch.

The motivation behind this patch is the existence of malicious devices.
Lots of research has been done about how to use the IOMMU as protection
from such devices.  When ATS is supported, any I/O device can access any
physical address by faking device-IOTLB entries.  Adding the ability to
ignore these entries lets sysadmins enhance system security.

Signed-off-by: Gil Kupfer &lt;gilkup@cs.technion.ac.il&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Joerg Roedel &lt;jroedel@suse.de&gt;</content>
</entry>
<entry>
<title>PCI: Tidy comments</title>
<updated>2018-03-19T19:20:43Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2018-03-09T22:36:33Z</published>
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<id>urn:sha1:df62ab5e0f75608919df7442654b0fab78246b7b</id>
<content type='text'>
Remove pointless comments that tell us the file name, remove blank line
comments, follow multi-line comment conventions.  No functional change
intended.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Add SPDX GPL-2.0 when no license was specified</title>
<updated>2018-01-26T17:45:16Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2018-01-26T17:45:16Z</published>
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<id>urn:sha1:7328c8f48d1895b3fec98b0b319cfb856b4c4fa1</id>
<content type='text'>
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") added SPDX GPL-2.0 to several PCI files that
previously contained no license information.

Add SPDX GPL-2.0 to all other PCI files that did not contain any license
information and hence were under the default GPL version 2 license of the
kernel.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;</content>
</entry>
<entry>
<title>PCI: Restore PRI and PASID state after Function-Level Reset</title>
<updated>2017-05-30T20:40:50Z</updated>
<author>
<name>CQ Tang</name>
</author>
<published>2017-05-30T16:25:49Z</published>
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<id>urn:sha1:4ebeb1ec56d4c54a56b6f43c2603d9a4688c83ba</id>
<content type='text'>
After a Function-Level Reset, PCI states need to be restored.  Save PASID
features and PRI reqs cached.

[bhelgaas: search for capability only if PRI/PASID were enabled]
Signed-off-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: Ashok Raj &lt;ashok.raj@intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: Jean-Phillipe Brucker &lt;jean-philippe.brucker@arm.com&gt;
Cc: David Woodhouse &lt;dwmw2@infradead.org&gt;</content>
</entry>
<entry>
<title>PCI: Cache PRI and PASID bits in pci_dev</title>
<updated>2017-05-30T20:39:15Z</updated>
<author>
<name>Jean-Philippe Brucker</name>
</author>
<published>2017-05-30T16:25:48Z</published>
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<id>urn:sha1:a4f4fa681add289ebfec6d776376ad7a2ffda669</id>
<content type='text'>
Device drivers need to check if an IOMMU enabled ATS, PRI and PASID in
order to know when they can use the SVM API.  Cache PRI and PASID bits in
the pci_dev structure, similarly to what is currently done for ATS.

Signed-off-by: Jean-Philippe Brucker &lt;jean-philippe.brucker@arm.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Remove pci_ats_enabled()</title>
<updated>2015-08-13T20:59:59Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2015-07-20T14:23:37Z</published>
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<id>urn:sha1:f7ef1340bb501717372a39f4807d0ad519ebd432</id>
<content type='text'>
Remove pci_ats_enabled().  There are no callers outside the ATS code
itself.  We don't need to check ats_cap, because if we don't find an ATS
capability, we'll never set ats_enabled.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Joerg Roedel &lt;jroedel@suse.de&gt;</content>
</entry>
<entry>
<title>PCI: Stop caching ATS Invalidate Queue Depth</title>
<updated>2015-08-13T20:59:58Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2015-07-20T14:24:32Z</published>
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<id>urn:sha1:a71f938f3a9a7bc879296cd34ecae9effe5edf3f</id>
<content type='text'>
Stop caching the Invalidate Queue Depth in struct pci_dev.
pci_ats_queue_depth() is typically called only once per device, and it
returns a fixed value per-device, so callers who need the value frequently
can cache it themselves.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Joerg Roedel &lt;jroedel@suse.de&gt;</content>
</entry>
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