<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/net/phy/mscc/mscc.h, branch linux-rolling-lts</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-rolling-lts</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-rolling-lts'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2025-08-29T18:48:01Z</updated>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net</title>
<updated>2025-08-29T18:48:01Z</updated>
<author>
<name>Jakub Kicinski</name>
</author>
<published>2025-06-12T17:08:24Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d23ad54de795ec0054f90ecb03b41e8f2c410f3a'/>
<id>urn:sha1:d23ad54de795ec0054f90ecb03b41e8f2c410f3a</id>
<content type='text'>
Cross-merge networking fixes after downstream PR (net-6.17-rc4).

No conflicts.

Adjacent changes:

drivers/net/ethernet/intel/idpf/idpf_txrx.c
  02614eee26fb ("idpf: do not linearize big TSO packets")
  6c4e68480238 ("idpf: remove obsolete stashing code")

Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: mscc: Fix when PTP clock is register and unregister</title>
<updated>2025-08-27T00:10:51Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2025-08-25T06:55:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=882e57cbc7204662f6c5672d5b04336c1d790b03'/>
<id>urn:sha1:882e57cbc7204662f6c5672d5b04336c1d790b03</id>
<content type='text'>
It looks like that every time when the interface was set down and up the
driver was creating a new ptp clock. On top of this the function
ptp_clock_unregister was never called.
Therefore fix this by calling ptp_clock_register and initialize the
mii_ts struct inside the probe function and call ptp_clock_unregister when
driver is removed.

Fixes: 7d272e63e0979d ("net: phy: mscc: timestamping and PHC support")
Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Reviewed-by: Vadim Fedorenko &lt;vadim.fedorenko@linux.dev&gt;
Reviewed-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Link: https://patch.msgid.link/20250825065543.2916334-1-horatiu.vultur@microchip.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net</title>
<updated>2025-08-21T18:33:15Z</updated>
<author>
<name>Jakub Kicinski</name>
</author>
<published>2025-06-12T17:08:24Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a9af709fda7edafa17e072bffe610d9e7ed7a5df'/>
<id>urn:sha1:a9af709fda7edafa17e072bffe610d9e7ed7a5df</id>
<content type='text'>
Cross-merge networking fixes after downstream PR (net-6.17-rc3).

No conflicts or adjacent changes.

Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: mscc: Fix timestamping for vsc8584</title>
<updated>2025-08-20T00:52:02Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2025-08-18T08:10:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bc1a59cff9f797bfbf8f3104507584d89e9ecf2e'/>
<id>urn:sha1:bc1a59cff9f797bfbf8f3104507584d89e9ecf2e</id>
<content type='text'>
There was a problem when we received frames and the frames were
timestamped. The driver is configured to store the nanosecond part of
the timestmap in the ptp reserved bits and it would take the second part
by reading the LTC. The problem is that when reading the LTC we are in
atomic context and to read the second part will go over mdio bus which
might sleep, so we get an error.
The fix consists in actually put all the frames in a queue and start the
aux work and in that work to read the LTC and then calculate the full
received time.

Fixes: 7d272e63e0979d ("net: phy: mscc: timestamping and PHC support")
Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Reviewed-by: Vadim Fedorenko &lt;vadim.fedorenko@linux.dev&gt;
Reviewed-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Link: https://patch.msgid.link/20250818081029.1300780-1-horatiu.vultur@microchip.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: report and configure in-band auto-negotiation for SGMII/QSGMII</title>
<updated>2025-08-15T00:42:32Z</updated>
<author>
<name>Vladimir Oltean</name>
</author>
<published>2025-08-13T07:44:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=df979273bd716a93ca9ffa8f84aeb205c9bf2ab6'/>
<id>urn:sha1:df979273bd716a93ca9ffa8f84aeb205c9bf2ab6</id>
<content type='text'>
The following Vitesse/Microsemi/Microchip PHYs, among those supported by
this driver, have the host interface configurable as SGMII or QSGMII:
- VSC8504
- VSC8514
- VSC8552
- VSC8562
- VSC8572
- VSC8574
- VSC8575
- VSC8582
- VSC8584

All these PHYs are documented to have bit 7 of "MAC SerDes PCS Control"
as "MAC SerDes ANEG enable".

Out of these, I could test the VSC8514 quad PHY in QSGMII. This works
both with the in-band autoneg on and off, on the NXP LS1028A-RDB and
T1040-RDB boards.

Notably, the bit is sticky (survives soft resets), so giving Linux the
tools to read and modify this settings makes it robust to changes made
to it by previous boot layers (U-Boot).

Signed-off-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Reviewed-by: Russell King (Oracle) &lt;rmk+kernel@armlinux.org.uk&gt;
Link: https://patch.msgid.link/20250813074454.63224-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: extend PHY package API to support multiple global address</title>
<updated>2023-12-17T20:10:07Z</updated>
<author>
<name>Christian Marangi</name>
</author>
<published>2023-12-15T13:15:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=9eea577eb1155fe4a183bc5e7bf269b0b2e7a6ba'/>
<id>urn:sha1:9eea577eb1155fe4a183bc5e7bf269b0b2e7a6ba</id>
<content type='text'>
Current API for PHY package are limited to single address to configure
global settings for the PHY package.

It was found that some PHY package (for example the qca807x, a PHY
package that is shipped with a bundle of 5 PHY) requires multiple PHY
address to configure global settings. An example scenario is a PHY that
have a dedicated PHY for PSGMII/serdes calibrarion and have a specific
PHY in the package where the global PHY mode is set and affects every
other PHY in the package.

Change the API in the following way:
- Change phy_package_join() to take the base addr of the PHY package
  instead of the global PHY addr.
- Make __/phy_package_write/read() require an additional arg that
  select what global PHY address to use by passing the offset from the
  base addr passed on phy_package_join().

Each user of this API is updated to follow this new implementation
following a pattern where an enum is defined to declare the offset of the
addr.

We also drop the check if shared is defined as any user of the
phy_package_read/write is expected to use phy_package_join first. Misuse
of this will correctly trigger a kernel panic for NULL pointer
exception.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>phy: mscc: Use PHY_ID_MATCH_VENDOR to minimize PHY ID table</title>
<updated>2023-06-01T05:33:45Z</updated>
<author>
<name>Harini Katakam</name>
</author>
<published>2023-05-29T12:20:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=31605c01fb242806f5b8c9d08abe11328d514206'/>
<id>urn:sha1:31605c01fb242806f5b8c9d08abe11328d514206</id>
<content type='text'>
All the PHY devices variants specified have the same mask and
hence can be simplified to one vendor look up for 0x00070400.
Any individual config can be identified by PHY_ID_MATCH_EXACT
in the respective structure.

Signed-off-by: Harini Katakam &lt;harini.katakam@amd.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: enable VSC8501/2 RGMII RX clock</title>
<updated>2023-05-25T05:14:23Z</updated>
<author>
<name>David Epping</name>
</author>
<published>2023-05-23T15:31:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=71460c9ec5c743e9ffffca3c874d66267c36345e'/>
<id>urn:sha1:71460c9ec5c743e9ffffca3c874d66267c36345e</id>
<content type='text'>
By default the VSC8501 and VSC8502 RGMII/GMII/MII RX_CLK output is
disabled. To allow packet forwarding towards the MAC it needs to be
enabled.

For other PHYs supported by this driver the clock output is enabled
by default.

Fixes: d3169863310d ("net: phy: mscc: add support for VSC8502")
Signed-off-by: David Epping &lt;david.epping@missinglinkelectronics.com&gt;
Reviewed-by: Russell King (Oracle) &lt;rmk+kernel@armlinux.org.uk&gt;
Reviewed-by: Vladimir Oltean &lt;olteanv@gmail.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: add support for VSC8501</title>
<updated>2023-05-25T05:14:10Z</updated>
<author>
<name>David Epping</name>
</author>
<published>2023-05-23T15:31:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fb055ce4a9e3a115f5dc42011a97cf0cfc7820e4'/>
<id>urn:sha1:fb055ce4a9e3a115f5dc42011a97cf0cfc7820e4</id>
<content type='text'>
The VSC8501 PHY can use the same driver implementation as the VSC8502.
Adding the PHY ID and copying the handler functions of VSC8502 is
sufficient to operate it.

Signed-off-by: David Epping &lt;david.epping@missinglinkelectronics.com&gt;
Reviewed-by: Vladimir Oltean &lt;olteanv@gmail.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: mscc: coma mode disabled for VSC8514</title>
<updated>2021-02-16T22:06:19Z</updated>
<author>
<name>Bjarni Jonasson</name>
</author>
<published>2021-02-16T15:29:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ca0d7fd0a58dfc9503775dae7daee341c115e0c7'/>
<id>urn:sha1:ca0d7fd0a58dfc9503775dae7daee341c115e0c7</id>
<content type='text'>
The 'coma mode' (configurable through sw or hw) provides an
optional feature that may be used to control when the PHYs become active.
The typical usage is to synchronize the link-up time across
all PHY instances. This patch releases coma mode if not done by hardware,
otherwise the phys will not link-up.

Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.")
Signed-off-by: Steen Hegelund &lt;steen.hegelund@microchip.com&gt;
Signed-off-by: Bjarni Jonasson &lt;bjarni.jonasson@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
</feed>
