<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/net/ipa/gsi.c, branch linux-5.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y</id>
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<updated>2021-06-21T19:30:59Z</updated>
<entry>
<title>net: ipa: introduce gsi_ring_setup()</title>
<updated>2021-06-21T19:30:59Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-06-21T17:56:26Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bae70a803a771d0f1e55cfe1db195d8af2765dd8'/>
<id>urn:sha1:bae70a803a771d0f1e55cfe1db195d8af2765dd8</id>
<content type='text'>
Prior to IPA v3.5.1, there is no HW_PARAM_2 GSI register, which we
use to determine the number of channels and endpoints per execution
environment.  In that case, we will just assume the number supported
is the maximum supported by the driver.

Introduce gsi_ring_setup() to encapsulate the code that determines
the number of channels and endpoints.

Update GSI_EVT_RING_COUNT_MAX so it is big enough to handle any
available channel for all supported hardware (IPA v4.9 can have 23
channels and 24 event rings).

Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Acked-by: AngeloGioacchino Del Regno
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: inter-EE interrupts aren't always available</title>
<updated>2021-06-21T19:30:59Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-06-21T17:56:23Z</published>
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<id>urn:sha1:c31d73494fa5016596f0b36aeb3e388160c9c473</id>
<content type='text'>
The GSI inter-EE interrupts are not supported prior to IPA v3.5.
Don't attempt to initialize them in gsi_irq_setup() for hardware
that does not support them.

Originally proposed by AngeloGioacchino Del Regno.

Link: https://lore.kernel.org/netdev/20210211175015.200772-4-angelogioacchino.delregno@somainline.org
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Acked-by: AngeloGioacchino Del Regno
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: fix inter-EE IRQ register definitions</title>
<updated>2021-05-06T23:32:10Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-05-05T22:36:36Z</published>
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<id>urn:sha1:6a780f51f87b430cc69ebf4e859e7e9be720b283</id>
<content type='text'>
In gsi_irq_setup(), two registers are written with the intention of
disabling inter-EE channel and event IRQs.

But the wrong registers are used (and defined); the ones used are
read-only registers that indicate whether the interrupt condition is
present.

Define the mask registers instead of the status registers, and use
them to disable the inter-EE interrupt types.

Fixes: 46f748ccaf01 ("net: ipa: explicitly disallow inter-EE interrupts")
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Link: https://lore.kernel.org/r/20210505223636.232527-1-elder@linaro.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: ipa: get rid of empty GSI functions</title>
<updated>2021-04-10T03:57:25Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-04-09T18:07:21Z</published>
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<id>urn:sha1:57ab8ca42fa07fdbd02828a0b90de704605f70cd</id>
<content type='text'>
There are place holder functions in the GSI code that do nothing.
Remove these, knowing we can add something back in their place if
they're really needed someday.

Some of these are inverse functions (such as teardown to match setup).
Explicitly comment that there is no inverse in these cases.

Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: ipa: DMA addresses are nicely aligned</title>
<updated>2021-03-29T01:12:03Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-03-28T17:31:10Z</published>
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<id>urn:sha1:19aaf72c0c7a26ab7ffc655a6d84da6a379f899b</id>
<content type='text'>
A recent patch avoided doing 64-bit modulo operations by checking
the alignment of some DMA allocations using only the lower 32 bits
of the address.

David Laight pointed out (after the fix was committed) that DMA
allocations might already satisfy the alignment requirements.  And
he was right.

Remove the alignment checks that occur after DMA allocation requests,
and update comments to explain why the constraint is satisfied.  The
only place IPA_TABLE_ALIGN was used was to check the alignment; it is
therefore no longer needed, so get rid of it.

Add comments where GSI_RING_ELEMENT_SIZE and the tre_count and
event_count channel data fields are defined to make explicit they
are required to be powers of 2.

Revise a comment in gsi_trans_pool_init_dma(), taking into account
that dma_alloc_coherent() guarantees its result is aligned to a page
size (or order thereof).

Don't bother printing an error if a DMA allocation fails.

Suggested-by: David Laight &lt;David.Laight@ACULAB.COM&gt;
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: expand GSI channel types</title>
<updated>2021-03-26T00:22:30Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-03-25T14:44:37Z</published>
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<id>urn:sha1:2ad6f03b59332cd875d20c52ab18bb6a927a3213</id>
<content type='text'>
IPA v4.5 (GSI v2.5) supports a larger set of channel protocols, and
adds an additional field to hold the most-significant bits of the
protocol identifier on a channel.

Add an inline function that encodes the protocol (including the
extra bits for newer versions of IPA), and define some additional
protocols.  At this point we still use only GPI protocol.

Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: update GSI ring size registers</title>
<updated>2021-03-26T00:22:30Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-03-25T14:44:36Z</published>
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<id>urn:sha1:42839f9585a00b53691bc56e6a238029f1466959</id>
<content type='text'>
Each GSI channel has a CNTXT_1 register that encodes the size of its
ring buffer.  The size of the field that records that is increased
starting at IPA v4.9.  Replace the use of a fixed-size field mask
with a new inline function that encodes that size value.

Similarly, the size of GSI event rings can be larger starting with
IPA v4.9, so create a function to encode that as well.

Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: reduce IPA version assumptions</title>
<updated>2021-03-24T23:52:47Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-03-24T13:15:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d7f3087b396d8aa4b4751b61fa8cbab82113bd59'/>
<id>urn:sha1:d7f3087b396d8aa4b4751b61fa8cbab82113bd59</id>
<content type='text'>
Modify conditional tests throughout the IPA code so they do not
assume that IPA v3.5.1 is the oldest version supported.  Also remove
assumptions that IPA v4.5 is the newest version of IPA supported.

Augment versions in comments with "+", to be clearer that the
comment applies to a version and subsequent versions.  (E.g.,
"present for IPA v4.2+" instead of just "present for v4.2".)

Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: avoid 64-bit modulus</title>
<updated>2021-03-24T00:15:23Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-03-23T01:05:05Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=437c78f976f5b39fc4b2a1c65903a229f55912dd'/>
<id>urn:sha1:437c78f976f5b39fc4b2a1c65903a229f55912dd</id>
<content type='text'>
It is possible for a 32 bit x86 build to use a 64 bit DMA address.

There are two remaining spots where the IPA driver does a modulo
operation to check alignment of a DMA address, and under certain
conditions this can lead to a build error on i386 (at least).

The alignment checks we're doing are for power-of-2 values, and this
means the lower 32 bits of the DMA address can be used.  This ensures
both operands to the modulo operator are 32 bits wide.

Reported-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Acked-by: Randy Dunlap &lt;rdunlap@infradead.org&gt; # build-tested
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ipa: use upper_32_bits()</title>
<updated>2021-03-18T23:20:34Z</updated>
<author>
<name>Alex Elder</name>
</author>
<published>2021-03-18T18:59:28Z</published>
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<id>urn:sha1:3c54b7be5d3677f37dfcd68afcc1d8e2b677a5b9</id>
<content type='text'>
Use upper_32_bits() to extract the high-order 32 bits of a DMA
address.  This avoids doing a 32-position shift on a DMA address
if it happens not to be 64 bits wide.  Use lower_32_bits() to
extract the low-order 32 bits (because that's what it's for).

Suggested-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: Alex Elder &lt;elder@linaro.org&gt;
Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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