<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/net/ethernet/xilinx, branch linux-5.4.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.4.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.4.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2025-08-28T14:21:16Z</updated>
<entry>
<title>net: emaclite: Fix missing pointer increment in aligned_read()</title>
<updated>2025-08-28T14:21:16Z</updated>
<author>
<name>Alok Tiwari</name>
</author>
<published>2025-07-10T17:38:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=04d49e2bc19870e3f7d1d18afe951bb6293a63a0'/>
<id>urn:sha1:04d49e2bc19870e3f7d1d18afe951bb6293a63a0</id>
<content type='text'>
[ Upstream commit 7727ec1523d7973defa1dff8f9c0aad288d04008 ]

Add missing post-increment operators for byte pointers in the
loop that copies remaining bytes in xemaclite_aligned_read().
Without the increment, the same byte was written repeatedly
to the destination.
This update aligns with xemaclite_aligned_write()

Fixes: bb81b2ddfa19 ("net: add Xilinx emac lite device driver")
Signed-off-by: Alok Tiwari &lt;alok.a.tiwari@oracle.com&gt;
Link: https://patch.msgid.link/20250710173849.2381003-1-alok.a.tiwari@oracle.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: xilinx: axienet: Fix dangling multicast addresses</title>
<updated>2024-09-04T11:15:00Z</updated>
<author>
<name>Sean Anderson</name>
</author>
<published>2024-08-22T15:40:56Z</published>
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<id>urn:sha1:1573f51ef1ed007ab39bad2d0992191e1a11496f</id>
<content type='text'>
[ Upstream commit 797a68c9de0f5a5447baf4bd3bb9c10a3993435b ]

If a multicast address is removed but there are still some multicast
addresses, that address would remain programmed into the frame filter.
Fix this by explicitly setting the enable bit for each filter.

Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Link: https://patch.msgid.link/20240822154059.1066595-3-sean.anderson@linux.dev
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: xilinx: axienet: Always disable promiscuous mode</title>
<updated>2024-09-04T11:15:00Z</updated>
<author>
<name>Sean Anderson</name>
</author>
<published>2024-08-22T15:40:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c66ed34257ae0bb9d3eb2b5c656f1f7fd5f4cb04'/>
<id>urn:sha1:c66ed34257ae0bb9d3eb2b5c656f1f7fd5f4cb04</id>
<content type='text'>
[ Upstream commit 4ae738dfef2c0323752ab81786e2d298c9939321 ]

If promiscuous mode is disabled when there are fewer than four multicast
addresses, then it will not be reflected in the hardware. Fix this by
always clearing the promiscuous mode flag even when we program multicast
addresses.

Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Link: https://patch.msgid.link/20240822154059.1066595-2-sean.anderson@linux.dev
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Fix register defines comment description</title>
<updated>2024-09-04T11:14:52Z</updated>
<author>
<name>Radhey Shyam Pandey</name>
</author>
<published>2024-08-09T06:26:09Z</published>
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<id>urn:sha1:d7fa0c35826a7e28702b94810cd20717da33a8d3</id>
<content type='text'>
[ Upstream commit 9ff2f816e2aa65ca9a1cdf0954842f8173c0f48d ]

In axiethernet header fix register defines comment description to be
inline with IP documentation. It updates MAC configuration register,
MDIO configuration register and frame filter control description.

Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@amd.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Autodetect 64-bit DMA capability</title>
<updated>2024-09-04T11:14:52Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2020-03-24T13:23:46Z</published>
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<id>urn:sha1:8b04b6b7c4e5dd16e7acb8b16e2659efb784373b</id>
<content type='text'>
[ Upstream commit f735c40ed93ccaeb52d026def47ac1a423df7133 ]

When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.

To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.

The actual DMA mask stays at 32-bit for now. To help bisecting, a
separate patch will enable allocations from higher addresses.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Upgrade descriptors to hold 64-bit addresses</title>
<updated>2024-09-04T11:14:52Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2020-03-24T13:23:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=46a5469f928c7215641f539ef99091d0923b2375'/>
<id>urn:sha1:46a5469f928c7215641f539ef99091d0923b2375</id>
<content type='text'>
[ Upstream commit 4e958f33ee8f404787711416fe0f78cce2b2f4e2 ]

Newer revisions of the AXI DMA IP (&gt;= v7.1) support 64-bit addresses,
both for the descriptors itself, as well as for the buffers they are
pointing to.
This is realised by adding "MSB" words for the next and phys pointer
right behind the existing address word, now named "LSB". These MSB words
live in formerly reserved areas of the descriptor.

If the hardware supports it, write both words when setting an address.
The buffer address is handled by two wrapper functions, the two
occasions where we set the next pointers are open coded.

For now this is guarded by a flag which we don't set yet.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Wrap DMA pointer writes to prepare for 64 bit</title>
<updated>2024-09-04T11:14:52Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2020-03-24T13:23:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=67527bcb0f677a812a0181e77dc3b70d8bc9d30e'/>
<id>urn:sha1:67527bcb0f677a812a0181e77dc3b70d8bc9d30e</id>
<content type='text'>
[ Upstream commit 6a00d0dd3fcfa2ef200973479fbeee62f3681130 ]

Newer versions of the Xilink DMA IP support busses with more than 32
address bits, by introducing an MSB word for the registers holding DMA
pointers (tail/current, RX/TX descriptor addresses).
On IP configured for more than 32 bits, it is also *required* to write
both words, to let the IP recognise this as a start condition for an
MM2S request, for instance.

Wrap the DMA pointer writes with a separate function, to add this
functionality later. For now we stick to the lower 32 bits.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Drop MDIO interrupt registers from ethtools dump</title>
<updated>2024-09-04T11:14:52Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2020-03-24T13:23:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2978228525a08b6a6d9f740fa2e87c1f029105d4'/>
<id>urn:sha1:2978228525a08b6a6d9f740fa2e87c1f029105d4</id>
<content type='text'>
[ Upstream commit c30cb8f0bec69d56e1fbc7fb65bd735c729a69e4 ]

Newer revisions of the IP don't have these registers. Since we don't
really use them, just drop them from the ethtools dump.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Check for DMA mapping errors</title>
<updated>2024-09-04T11:14:52Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2020-03-24T13:23:40Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d724554f8ff642708f8d351052cab39b7bb49ed6'/>
<id>urn:sha1:d724554f8ff642708f8d351052cab39b7bb49ed6</id>
<content type='text'>
[ Upstream commit 71791dc8bdea55eeb2a0caefe98a0b7450c6e0af ]

Especially with the default 32-bit DMA mask, DMA buffers are a limited
resource, so their allocation can fail.
So as the DMA API documentation requires, add error checking code after
dma_map_single() calls to catch the case where we run out of "low" memory.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: axienet: Factor out TX descriptor chain cleanup</title>
<updated>2024-09-04T11:14:51Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2020-03-24T13:23:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=367ca46817b702c596c6fc6d68b01d60c8ff85b1'/>
<id>urn:sha1:367ca46817b702c596c6fc6d68b01d60c8ff85b1</id>
<content type='text'>
[ Upstream commit ab365c3393664f32116aa22fe322cb04a93fab31 ]

Factor out the code that cleans up a number of connected TX descriptors,
as we will need it to properly roll back a failed _xmit() call.
There are subtle differences between cleaning up a successfully sent
chain (unknown number of involved descriptors, total data size needed)
and a chain that was about to set up (number of descriptors known), so
cater for those variations with some extra parameters.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
</feed>
