kernel.git/drivers/mfd/lpc_ich.c, branch linux-5.18.y

mtd: spi-nor: intel-spi: Disable write protection only if asked

2022-02-14T12:53:08Z

Currently the driver tries to disable the BIOS write protection automatically even if this is not what the user wants. For this reason modify the driver so that by default it does not touch the write protection. Only if specifically asked by the user (setting writeable=1 command line parameter) the driver tries to disable the BIOS write protection. Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko Reviewed-by: Mauro Lima Reviewed-by: Tudor Ambarus Acked-by: Lee Jones Link: https://lore.kernel.org/r/20220209122706.42439-2-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown

mfd: lpc_ich: Enable GPIO driver for DH89xxCC

2021-07-20T14:46:51Z

Based on the Intel Datasheet for the DH89xxCC PCH, the GPIO driver is the same as ICH_v5_GPIO, minus the fact the DH89xxCC also has blink support. However, blink support isn't supported by the GPIO driver so we should use ICH_v5_GPIO. Tested and working on a Meraki MX100-HW. Signed-off-by: Chris Blake Co-developed-by: Christian Lamparter Signed-off-by: Lee Jones

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 294

2019-06-05T15:36:38Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation this program is distributed in the hope that it [would] be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 9 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Alexios Zavras Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.804956444@linutronix.de Signed-off-by: Greg Kroah-Hartman

mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Apollo Lake

2018-01-08T11:03:35Z

Just to be on the safe side, don't touch the bit. If write access to the flash chip is needed, the BIOS needs to enable it explicitly. Signed-off-by: Mika Westerberg Signed-off-by: Lee Jones

mfd: lpc_ich: Avoton/Rangeley uses SPI_BYT method

2017-10-24T08:12:03Z

Avoton/Rangeley are based on Silvermount micro-architecture, like Bay Trail, and uses the INTEL_SPI_BYT method to drive SPI. Cc: stable@vger.kernel.org Signed-off-by: Joakim Tjernlund Acked-by: Mika Westerberg Signed-off-by: Lee Jones

mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell

2017-09-05T07:46:01Z

At least on Lenovo Thinkpad Yoga, the BIOS seems to monitor the SPI-NOR write protection bit and if it is flipped to read/write it assumes the BIOS configuration was changed on next reboot. It then, for unknown reasons, resets the BIOS settings back to default. We can prevent this by just leaving the write protection bit intact and let the SPI-NOR driver know whether the device is writable or not. In case of this particular Lenovo the SPI-NOR flash will be exposed as read-only. Fixes: ff00d7a32a1b ("mfd: lpc_ich: Add support for SPI serial flash host controller") Link: https://bugzilla.kernel.org/show_bug.cgi?id=195951 Reported-by: Abdó Roig-Marange Signed-off-by: Mika Westerberg Signed-off-by: Lee Jones

mfd: lpc_ich: Add support for Intel Gemini Lake SoC

2017-04-27T10:54:43Z

Like Intel Apollo Lake, Gemini Lake exposes the serial SPI flash device BAR through hidden P2SB PCI device. We use the same mechanism than Apollo Lake to read the BAR and pass it to the driver. Signed-off-by: Mika Westerberg Signed-off-by: Lee Jones

mfd: lpc_ich: Add PCI ID for Intel Cougar Mountain SoC

2017-04-27T08:25:03Z

This patches adds the first minimal support to the upstream Linux tree. Signed-off-by: Priyalee Kushwaha Signed-off-by: Alan Cox Signed-off-by: Lee Jones

mfd: lpc_ich: Enable watchdog on Intel Apollo Lake PCH

2017-02-13T09:29:44Z

Assign iTCO_version which effectively enables watchdog device on Intel Apollo Lake PCH. Signed-off-by: Tan Jui Nee Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Lee Jones

mfd: lpc_ich: Remove useless comments in core part

2017-02-13T09:29:44Z

First of all, remove stalled references to datasheets. If someone knows the document numbers, it would be added later. Second, remove FSF snail address since it's subject to change. Actual information can be found on FSF site on the internet. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Lee Jones