<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/mfd/lpc_ich.c, branch linux-4.0.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.0.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.0.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2014-09-26T07:15:44Z</updated>
<entry>
<title>mfd: lpc_ich: Add Device IDs for Intel 9 Series PCH</title>
<updated>2014-09-26T07:15:44Z</updated>
<author>
<name>James Ralston</name>
</author>
<published>2014-08-27T21:34:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fea31042ff613145c7784e2ce454bf3c151b97ba'/>
<id>urn:sha1:fea31042ff613145c7784e2ce454bf3c151b97ba</id>
<content type='text'>
This patch adds the LPC Device IDs for the Intel 9 Series PCH.

Signed-off-by: James Ralston &lt;james.d.ralston@intel.com&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Add PCI ID for Intel Braswell</title>
<updated>2014-09-26T07:15:42Z</updated>
<author>
<name>Alan Cox</name>
</author>
<published>2014-08-21T09:46:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ff0c9da013d2c9f1ec232926a54e536ab48c6678'/>
<id>urn:sha1:ff0c9da013d2c9f1ec232926a54e536ab48c6678</id>
<content type='text'>
This is the same as used in Baytrail so add the new PCI ID to the driver's
list of supported IDs.

Signed-off-by: Alan Cox &lt;alan@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Enable GPIO for Panther Point</title>
<updated>2014-06-03T07:11:15Z</updated>
<author>
<name>Guenter Roeck</name>
</author>
<published>2014-04-05T15:49:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=62cf2cdb99c7e870ab857bdd617e728790f8c43c'/>
<id>urn:sha1:62cf2cdb99c7e870ab857bdd617e728790f8c43c</id>
<content type='text'>
Panther Point PCH GPIO configuration is similar to V5 PCHs.

Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Add support for Intel Bay Trail SoC</title>
<updated>2014-03-19T09:00:05Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6111ec70357022ccd037399c13f69900431850b4'/>
<id>urn:sha1:6111ec70357022ccd037399c13f69900431850b4</id>
<content type='text'>
This patch adds the LPC Controller Device IDs for Watchdog and GPIO for
the Intel Bay Trail Atom SoC.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Add support for NM10 GPIO</title>
<updated>2014-03-19T09:00:04Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:57Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=117bbfe25cfc2e968be1f7976ac460a5cd3d734e'/>
<id>urn:sha1:117bbfe25cfc2e968be1f7976ac460a5cd3d734e</id>
<content type='text'>
The NM10's GPIO is compatible with ICH v7 GPIO.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Dan Weinlader &lt;danw@vs-networks.com&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Change Avoton to iTCO v3</title>
<updated>2014-03-19T09:00:03Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c48cf59878685cc06b71bb2a3ca17b61103c8de7'/>
<id>urn:sha1:c48cf59878685cc06b71bb2a3ca17b61103c8de7</id>
<content type='text'>
The register layout of the Avoton is compatible with the iTCO v3
register layout.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Rajat Jain &lt;rajatjain@juniper.net&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Add support for iTCO v3</title>
<updated>2014-03-19T09:00:02Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=eb71d4dec4a5e010e34b9d7afdb5af41884c388e'/>
<id>urn:sha1:eb71d4dec4a5e010e34b9d7afdb5af41884c388e</id>
<content type='text'>
Some newer Atom CPUs, eg Avoton and Bay Trail, use slightly different
register layouts for the iTCO than the current v1 and v2 iTCO.
Differences from previous iTCO versions include:
- The ACPI space is enabled in the "ACPI base address" register instead
  of the "ACPI control register"

- The "no reboot" functionality is set in the "Power Management
  Configuration" register instead of the "General Control and Status"
  (GCS) register or PCI configuration space.

- The "ACPI Control Register" is not present on v3.  The "Power
  Management Configuration Base Address" register resides at the same
  address is Avoton/Bay Trail.

To differentiate these newer chipsets create a new v3 iTCO version and
update the MFD driver to support them.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Rajat Jain &lt;rajatjain@juniper.net&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Remove lpc_ich_cfg struct use</title>
<updated>2014-03-19T09:00:01Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:53Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=429b941abd503c8936e116c819362323aafdbd50'/>
<id>urn:sha1:429b941abd503c8936e116c819362323aafdbd50</id>
<content type='text'>
Future chipsets will use different register layouts that don't map
cleanly to the lpc_ich_cfg fields.  Remove the lpc_ich_cfg struct and
add explicit fields to the higher level lpc_ich_priv structure.

This change should have no functional impact.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Rajat Jain &lt;rajatjain@juniper.net&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Only configure watchdog or GPIO when present</title>
<updated>2014-03-19T09:00:00Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:52Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f0776b8ce03ceb638c51b62f324844c71c446600'/>
<id>urn:sha1:f0776b8ce03ceb638c51b62f324844c71c446600</id>
<content type='text'>
Some chipsets don't currently have GPIO support enabled.  For these
chipsets don't go through the process of initializing the GPIO region.

Make the same change for the watchdog initialization for chipsets which
may not enable the WDT in the future.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Rajat Jain &lt;rajatjain@juniper.net&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Fix ACPI enable bitmask</title>
<updated>2014-03-19T09:00:00Z</updated>
<author>
<name>Peter Tyser</name>
</author>
<published>2014-03-10T21:34:51Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f5dccb15877b82a40950c6f752d5345c86189fc9'/>
<id>urn:sha1:f5dccb15877b82a40950c6f752d5345c86189fc9</id>
<content type='text'>
The original bitmask of 0x10 was incorrect and would result in a write
to a reserved read-only bit instead of enabling the ACPI I/O
region.  Update it to the proper value of 0x80.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Rajat Jain &lt;rajatjain@juniper.net&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
</feed>
