kernel.git/drivers/iio/dac/Makefile, branch linux-6.16.y

iio: dac: ad3530r: Add driver for AD3530R and AD3531R

2025-05-21T13:20:29Z

The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power, 16-bit, buffered voltage output DACs with software- programmable gain controls, providing full-scale output spans of 2.5V or 5V for reference voltages of 2.5V. These devices operate from a single 2.7V to 5.5V supply and are guaranteed monotonic by design. The "R" variants include a 2.5V, 5ppm/°C internal reference, which is disabled by default. Support for monitoring internal die temperature, output voltages, and current of a selected channel via the MUXOUT pin using an external ADC is currently not implemented. Reviewed-by: David Lechner Signed-off-by: Kim Seer Paller Reviewed-by: Andy Shevchenko Link: https://patch.msgid.link/20250429-togreg-v7-3-0af9c543b545@analog.com Signed-off-by: Jonathan Cameron

iio: dac: Support ROHM BD79703 DAC

2024-12-28T14:28:14Z

The ROHM BD79703 is a 6 channel digital to analog converter. Based on the data-sheet examples the hardware would support setting the DAC word without changing the actual output. The data-sheet is not too specific on how the enabling the output of new voltage set by DAC should be done - hence this is not implemented by the driver. The BD79703 would also support two specific "PULL_DOWN" modes. These aren't currently supported by the driver either. Add a very basic support for controlling the channel outputs one-by-one. Signed-off-by: Matti Vaittinen Link: https://patch.msgid.link/bc77d7b979ca28408a216f597082fcd94ec63be7.1734608215.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron

iio: dac: ad3552r: add high-speed platform driver

2024-11-03T20:33:32Z

Add High Speed ad3552r platform driver. The ad3552r DAC is controlled by a custom (fpga-based) DAC IP through the current AXI backend, or similar alternative IIO backend. Compared to the existing driver (ad3552r.c), that is a simple SPI driver, this driver is coupled with a DAC IIO backend that finally controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach maximum transfer rate of 33MUPS using dma stream capabilities. All commands involving QSPI bus read/write are delegated to the backend through the provided APIs for bus read/write. Reviewed-by: Nuno Sa Signed-off-by: Angelo Dureghello Reviewed-by: David Lechner Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-7-f6960b4f9719@kernel-space.org Signed-off-by: Jonathan Cameron

iio: dac: ad3552r: extract common code (no changes in behavior intended)

2024-11-01T14:54:48Z

Extracting common code, to share common code to be used later by the AXI driver version (ad3552r-axi.c). Signed-off-by: Angelo Dureghello Reviewed-by: David Lechner Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-6-f6960b4f9719@kernel-space.org Signed-off-by: Jonathan Cameron

iio: dac: support the ad8460 Waveform DAC

2024-09-30T08:21:03Z

The AD8460 is a “bits in, power out” high voltage, high-power, high-speed driver optimized for large output current (up to ±1 A) and high slew rate (up to ±1800 V/μs) at high voltage (up to ±40 V) into capacitive loads. A digital engine implements user-configurable features: modes for digital input, programmable supply current, and fault monitoring and programmable protection settings for output current, output voltage, and junction temperature. The AD8460 operates on high voltage dual supplies up to ±55 V and a single low voltage supply of 5 V. Signed-off-by: Mariel Tinaco Link: https://patch.msgid.link/20240912095435.18639-3-Mariel.Tinaco@analog.com Signed-off-by: Jonathan Cameron

iio: dac: ltc2664: Add driver for LTC2664 and LTC2672

2024-08-03T09:13:37Z

LTC2664 4 channel, 12-/16-Bit Voltage Output SoftSpan DAC LTC2672 5 channel, 12-/16-Bit Current Output Softspan DAC Reviewed-by: Nuno Sa Co-developed-by: Michael Hennerich Signed-off-by: Michael Hennerich Signed-off-by: Kim Seer Paller Reviewed-by: Conor Dooley Link: https://patch.msgid.link/20240718051834.32270-7-kimseer.paller@analog.com Signed-off-by: Jonathan Cameron

iio: dac: support the ad9739a RF DAC

2024-04-20T14:41:32Z

The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from DC up to 3 GHz. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. Co-developed-by: Dragos Bogdan Signed-off-by: Dragos Bogdan Signed-off-by: Nuno Sa Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-10-5ca45b4de294@analog.com Signed-off-by: Jonathan Cameron

iio: dac: add support for AXI DAC IP core

2024-04-20T14:41:32Z

Support the Analog Devices Generic AXI DAC IP core. The IP core is used for interfacing with digital-to-analog (DAC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Typically (for such devices) SPI will be used for configuration only, while this IP core handles the streaming of data into memory via DMA. Signed-off-by: Nuno Sa Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-9-5ca45b4de294@analog.com Signed-off-by: Jonathan Cameron

iio: dac: driver for MCP4821

2023-12-21T17:04:42Z

Adds driver for the MCP48xx series of DACs. Device uses a simplex SPI channel. To set the value of an output channel, a 16-bit data of following format must be written: Bit field | Description 15 [MSB] | Channel selection bit 0 -> Channel A 1 -> Channel B 13 | Output Gain Selection bit 0 -> 2x Gain (Vref = 4.096V) 1 -> 1x Gain (Vref = 2.048V) 12 | Output Shutdown Control bit 0 -> Shutdown the selected channel 1 -> Active mode operation 11-0 [LSB]| DAC Input Data bits Value's big endian representation is taken as input for the selected DAC channel. For devices with a resolution of less than 12-bits, only the x most significant bits are considered where x is the resolution of the device. Reference: Page#22 [MCP48x2 Datasheet] Supported devices: +---------+--------------+-------------+ | Device | Resolution | Channels | |---------|--------------|-------------| | MCP4801 | 8-bit | 1 | | MCP4802 | 8-bit | 2 | | MCP4811 | 10-bit | 1 | | MCP4812 | 10-bit | 2 | | MCP4821 | 12-bit | 1 | | MCP4822 | 12-bit | 2 | +---------+--------------+-------------+ Devices tested: MCP4821 [12-bit single channel] MCP4802 [8-bit dual channel] Tested on Raspberry Pi Zero 2W Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22244B.pdf #MCP48x1 Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20002249B.pdf #MCP48x2 Signed-off-by: Anshul Dalal Link: https://lore.kernel.org/r/20231220151954.154595-2-anshulusr@gmail.com Signed-off-by: Jonathan Cameron

iio: add MCP4728 I2C DAC driver

2023-08-05T18:29:39Z

MCP4728 is a 12-bit quad channel DAC with I2C interface. support for: * per-channel gain * per-channel power state * per-channel power down mode control * per-channel vref selection internal/vdd * store current state to on-chip EEPROM Signed-off-by: Andrea Collamati Link: https://lore.kernel.org/r/a0933003ed3c855f9d80d6ce0a40add2b6f0ba36.1691066050.git.andrea.collamati@gmail.com Signed-off-by: Jonathan Cameron