kernel.git/drivers/iio/dac/Kconfig, branch master

iio: dac: Add MAX22007 DAC driver support

2026-01-23T08:15:00Z

Add support for the MAX22007 4 channel DAC that drives a voltage or current output on each channel. Signed-off-by: Janani Sunil Signed-off-by: Jonathan Cameron

iio: dac: adding support for Microchip MCP47FEB02

2025-12-31T17:59:18Z

This is the iio driver for Microchip MCP47F(E/V)B(0/1/2)1, MCP47F(E/V)B(0/1/2)2, MCP47F(E/V)B(0/1/2)4 and MCP47F(E/V)B(0/1/2)8 series of buffered voltage output Digital-to-Analog Converters with nonvolatile or volatile memory and an I2C Interface. The families support up to 8 output channels. The devices can be 8-bit, 10-bit and 12-bit. Signed-off-by: Ariana Lazar Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron

iio: dac: ad5446: Separate I2C/SPI into different drivers

2025-11-09T16:15:13Z

Properly separate the I2C and SPI drivers into two different drivers living in their own source file (as usual). So that no need for the hacky ifdefery. Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron

iio: dac: ad3530r: Add driver for AD3530R and AD3531R

2025-05-21T13:20:29Z

The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power, 16-bit, buffered voltage output DACs with software- programmable gain controls, providing full-scale output spans of 2.5V or 5V for reference voltages of 2.5V. These devices operate from a single 2.7V to 5.5V supply and are guaranteed monotonic by design. The "R" variants include a 2.5V, 5ppm/°C internal reference, which is disabled by default. Support for monitoring internal die temperature, output voltages, and current of a selected channel via the MUXOUT pin using an external ADC is currently not implemented. Reviewed-by: David Lechner Signed-off-by: Kim Seer Paller Reviewed-by: Andy Shevchenko Link: https://patch.msgid.link/20250429-togreg-v7-3-0af9c543b545@analog.com Signed-off-by: Jonathan Cameron

iio: dac: ad5791: Add offload support

2025-02-11T19:32:31Z

Add SPI offload support to stream TX buffers using DMA. This allows loading samples to the DAC with a rate of 1 MSPS. Signed-off-by: Axel Haslam Reviewed-by: Jonathan Cameron Reviewed-by: Nuno Sa Signed-off-by: David Lechner Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-17-e48a489be48c@baylibre.com Signed-off-by: Jonathan Cameron

iio: dac: Support ROHM BD79703 DAC

2024-12-28T14:28:14Z

The ROHM BD79703 is a 6 channel digital to analog converter. Based on the data-sheet examples the hardware would support setting the DAC word without changing the actual output. The data-sheet is not too specific on how the enabling the output of new voltage set by DAC should be done - hence this is not implemented by the driver. The BD79703 would also support two specific "PULL_DOWN" modes. These aren't currently supported by the driver either. Add a very basic support for controlling the channel outputs one-by-one. Signed-off-by: Matti Vaittinen Link: https://patch.msgid.link/bc77d7b979ca28408a216f597082fcd94ec63be7.1734608215.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron

iio: dac: Fix converters spelling typo.

2024-12-07T17:47:58Z

Correct the converters typo error "convertors" => "converters" Signed-off-by: Karan Sanghavi Link: https://patch.msgid.link/20241111-dackconfigcodespell-v1-1-2498567be34c@gmail.com Signed-off-by: Jonathan Cameron

Merge commit '9365f0de4303f82ed4c2db1c39d3de824b249d80' into HEAD

2024-11-09T10:39:52Z

Merge v6.12-rc6 via char-misc-next to get some fixes needed for next few patches in IIO.

Merge 6.12-rc6 into char-misc-next

2024-11-05T08:36:29Z

We need the char/misc/iio fixes in here as well. Signed-off-by: Greg Kroah-Hartman

iio: dac: ad3552r: add high-speed platform driver

2024-11-03T20:33:32Z

Add High Speed ad3552r platform driver. The ad3552r DAC is controlled by a custom (fpga-based) DAC IP through the current AXI backend, or similar alternative IIO backend. Compared to the existing driver (ad3552r.c), that is a simple SPI driver, this driver is coupled with a DAC IIO backend that finally controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach maximum transfer rate of 33MUPS using dma stream capabilities. All commands involving QSPI bus read/write are delegated to the backend through the provided APIs for bus read/write. Reviewed-by: Nuno Sa Signed-off-by: Angelo Dureghello Reviewed-by: David Lechner Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-7-f6960b4f9719@kernel-space.org Signed-off-by: Jonathan Cameron