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<title>kernel.git/drivers/gpu/nova-core/gsp/fw.rs, branch master</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
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<updated>2026-03-11T15:24:15Z</updated>
<entry>
<title>gpu: nova-core: gsp: fix UB in DmaGspMem pointer accessors</title>
<updated>2026-03-11T15:24:15Z</updated>
<author>
<name>Danilo Krummrich</name>
</author>
<published>2026-03-09T22:53:24Z</published>
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<id>urn:sha1:0073a17b466684413ac87cf8ff6c19560db44e7a</id>
<content type='text'>
The DmaGspMem pointer accessor methods (gsp_write_ptr, gsp_read_ptr,
cpu_read_ptr, cpu_write_ptr, advance_cpu_read_ptr,
advance_cpu_write_ptr) dereference a raw pointer to DMA memory, creating
an intermediate reference before calling volatile read/write methods.

This is undefined behavior since DMA memory can be concurrently modified
by the device.

Fix this by moving the implementations into a gsp_mem module in fw.rs
that uses the dma_read!() / dma_write!() macros, making the original
methods on DmaGspMem thin forwarding wrappers.

An alternative approach would have been to wrap the shared memory in
Opaque, but that would have required even more unsafe code.

Since the gsp_mem module lives in fw.rs (to access firmware-specific
binding field names), GspMem, Msgq and their relevant fields are
temporarily widened to pub(super). This will be reverted once IoView
projections are available.

Cc: Gary Guo &lt;gary@garyguo.net&gt;
Closes: https://lore.kernel.org/nouveau/DGUT14ILG35P.1UMNRKU93JUM1@kernel.org/
Fixes: 75f6b1de8133 ("gpu: nova-core: gsp: Add GSP command queue bindings and handling")
Reviewed-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Link: https://patch.msgid.link/20260309225408.27714-1-dakr@kernel.org
[ Use pub(super) where possible; replace bitwise-and with modulo
  operator analogous to [1]. - Danilo ]
Link: https://lore.kernel.org/all/20260129-nova-core-cmdq1-v3-1-2ede85493a27@nvidia.com/ [1]
Signed-off-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: align LibosMemoryRegionInitArgument size to page size</title>
<updated>2026-01-24T01:48:59Z</updated>
<author>
<name>Alexandre Courbot</name>
</author>
<published>2026-01-22T22:28:46Z</published>
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<id>urn:sha1:58d26d42818c0f8c9b334cc7cf318b43046e675f</id>
<content type='text'>
On Turing and GA100 (i.e. the versions that use Libos v2), GSP-RM insists
that the 'size' parameter of the LibosMemoryRegionInitArgument struct be
aligned to 4KB.  The logging buffers are already aligned to that size, so
only the GSP_ARGUMENTS_CACHED struct needs to be adjusted.  Make that
adjustment by adding padding to the end of the struct.

Signed-off-by: Timur Tabi &lt;ttabi@nvidia.com&gt;
Reviewed-by: Gary Guo &lt;gary@garyguo.net&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20260122222848.2555890-12-ttabi@nvidia.com
[acourbot@nvidia.com: GspArgumentsAligned -&gt; GspArgumentsPadded]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: gsp: replace firmware version with "bindings" alias</title>
<updated>2025-12-16T13:04:25Z</updated>
<author>
<name>Alexandre Courbot</name>
</author>
<published>2025-12-16T02:57:10Z</published>
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<id>urn:sha1:b58c87b0fde0ac06d550659a7e3ddbcd9183b7b9</id>
<content type='text'>
We have an "bindings" alias to avoid having to mention the firmware
version again and again, and limit the diff when upgrading the firmware.
Use it where we neglected to.

Fixes: eaf0989c77e4 ("gpu: nova-core: Add bindings required by GSP sequencer")
Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Reviewed-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20251216-nova-fixes-v3-4-c7469a71f7c4@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: bindings: derive `MaybeZeroable`</title>
<updated>2025-12-16T13:04:25Z</updated>
<author>
<name>Alexandre Courbot</name>
</author>
<published>2025-12-16T02:57:09Z</published>
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<id>urn:sha1:523317152c4b1b3187d14c65ceacdfc0da451931</id>
<content type='text'>
Commit 4846300ba8f9 ("rust: derive `Zeroable` for all structs &amp; unions
generated by bindgen where possible") automatically derives
`MaybeZeroable` for all bindings. This is better than selectively
deriving `Zeroable` as it ensures all types that can implement
`Zeroable` do.

Regenerate the nova-core bindings so they benefit from this, and remove
a now unneeded implementation of `Zeroable`.

Fixes: 75f6b1de8133 ("gpu: nova-core: gsp: Add GSP command queue bindings and handling")
Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Reviewed-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20251216-nova-fixes-v3-3-c7469a71f7c4@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: gsp: fix length of received messages</title>
<updated>2025-12-16T13:03:48Z</updated>
<author>
<name>Alexandre Courbot</name>
</author>
<published>2025-12-16T02:57:08Z</published>
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<id>urn:sha1:9d250ab0cf80deb11148efe862d1184ebf5115f6</id>
<content type='text'>
The size of messages' payload is miscalculated, leading to extra data
passed to the message handler. While this is not a problem with our
current set of commands, others with a variable-length payload may
misbehave. Fix this by introducing a method returning the payload size
and using it.

Fixes: 75f6b1de8133 ("gpu: nova-core: gsp: Add GSP command queue bindings and handling")
Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Reviewed-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Reviewed-by: Alistair Popple &lt;apopple@nvidia.com&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20251216-nova-fixes-v3-2-c7469a71f7c4@nvidia.com
[acourbot@nvidia.com: update `PANIC:` comments as pointed out by Joel.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: make formatting compatible with rust tree</title>
<updated>2025-11-17T12:56:36Z</updated>
<author>
<name>Alice Ryhl</name>
</author>
<published>2025-11-17T10:39:17Z</published>
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<id>urn:sha1:77b686f688126a5f758b51441a03186e9eb1b0f1</id>
<content type='text'>
Commit 38b7cc448a5b ("gpu: nova-core: implement Display for Spec") in
drm-rust-next introduced some usage of the Display trait, but the
Display trait is being modified in the rust tree this cycle. Thus, to
avoid conflicts with the Rust tree, tweak how the formatting machinery
is used in a way where it works both with and without the changes in the
Rust tree.

Reviewed-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Tested-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Link: https://patch.msgid.link/20251117-nova-fmt-rust-v1-1-651ca28cd98f@google.com
Signed-off-by: Alice Ryhl &lt;aliceryhl@google.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: sequencer: Add delay opcode support</title>
<updated>2025-11-15T12:54:18Z</updated>
<author>
<name>Joel Fernandes</name>
</author>
<published>2025-11-14T19:55:48Z</published>
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<id>urn:sha1:e386680e8dbb37ff2973a2cbcf7124899e5359df</id>
<content type='text'>
Implement a sequencer opcode for delay operations.

Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-10-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: sequencer: Add register opcodes</title>
<updated>2025-11-15T12:54:18Z</updated>
<author>
<name>Joel Fernandes</name>
</author>
<published>2025-11-14T19:55:47Z</published>
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<id>urn:sha1:2367ce2e9e5eae3bfe72ed79a7fbd86936158569</id>
<content type='text'>
These opcodes are used for register write, modify, poll and store (save)
sequencer operations.

Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
[acourbot@nvidia.com: apply Lyude's suggested fixes.]
Message-ID: &lt;20251114195552.739371-9-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: Implement the GSP sequencer</title>
<updated>2025-11-15T12:05:50Z</updated>
<author>
<name>Joel Fernandes</name>
</author>
<published>2025-11-14T19:55:46Z</published>
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<id>urn:sha1:6ddfc892a529cb314e4708c5654beb0fa37e2071</id>
<content type='text'>
Implement the GSP sequencer which culminates in INIT_DONE message being
received from the GSP indicating that the GSP has successfully booted.

This is just initial sequencer support, the actual commands will be
added in the next patches.

Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
[acourbot@nvidia.com: move GspSequencerInfo definition before its impl
blocks and rename it to GspSequence, adapt imports in sequencer.rs to
new formatting rules, remove `timeout` argument to harmonize with other
commands.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-8-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: Add bindings required by GSP sequencer</title>
<updated>2025-11-15T11:35:50Z</updated>
<author>
<name>Joel Fernandes</name>
</author>
<published>2025-11-14T19:55:45Z</published>
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<id>urn:sha1:eaf0989c77e434ce491b2ed70ef505d8cf1d1d4b</id>
<content type='text'>
Add several firmware bindings required by GSP sequencer code.

Co-developed-by: Alistair Popple &lt;apopple@nvidia.com&gt;
Signed-off-by: Alistair Popple &lt;apopple@nvidia.com&gt;
Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
[acourbot@nvidia.com: remove a couple stray lines/unwanted comment
changes.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-7-joelagnelf@nvidia.com&gt;
</content>
</entry>
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