kernel.git/drivers/gpu/ipu-v3/ipu-common.c, branch linux-4.12.y

gpu: ipu-v3: Fix CSI selection for VDIC

2017-06-06T08:21:34Z

The description of the CSI_SEL bit in the i.MX6 reference manual is incorrect. It states "This bit defines which CSI is the input to the IC. This bit is effective only if IC_INPUT is bit cleared". From experiment it was found this is in fact not correct. The CSI_SEL bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC receives from in that case. Signed-off-by: Marek Vasut Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: don't depend on DRM being enabled

2017-04-04T08:58:56Z

The PRE/PRG drivers, which need the DRM infrastructure, are only used from the output path, so we skip building them into the ipu-v3 driver if CONFIG_DRM is not enabled. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: hook up PRG unit

2017-03-16T09:14:39Z

The i.MX6 QuadPlus IPU needs to PRG unit to gain access to the data bus. Make sure it is present and available to be used. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: add driver for Prefetch Resolve Gasket

2017-03-16T09:14:02Z

This adds support for the i.MX6 QUadPlus PRG unit. It glues together the IPU and the PRE units. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel --- v4: add missing ipu_soc->prg_priv

gpu: ipu-v3: add driver for Prefetch Resolve Engine

2017-03-15T14:42:35Z

This adds support for the i.MX6 QuadPlus PRE units. Currently only linear prefetch into SRAM is supported, other modes of operation like the tiled-to-linear conversion will be added later. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: add support for separate alpha channels

2017-03-15T14:42:31Z

The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven by the Alpha Transparency Controller (ATC) for the graphics IDMAC channels. This allows to reduce memory bandwidth via a conditional read mechanism or to support planar YUV formats with alpha transparency. Signed-off-by: Philipp Zabel

gpu: ipu-v3: add unsynchronised DP channel disabling

2017-03-15T14:28:27Z

When disabling the foreground DP channel during a modeset, the DC is already disabled without waiting for end of frame. There is no reason to wait for a frame boundary before updating the DP registers in that case. Add support to apply updates immediately. No functional changes, yet. Signed-off-by: Philipp Zabel Reviewed-by: Lucas Stach

gpu: ipu-v3: Stop overwriting pdev->dev.of_node of child devices

2017-02-17T07:04:27Z

Setting dev->of_node changes the modalias and breaks module autoloading. Since there is an of_node field in the platform data passed to child devices, we don't even need this anymore. Suggested-by: Russell King Signed-off-by: Philipp Zabel

gpu: ipu-v3: initially clear all interrupts

2016-10-20T12:40:21Z

If we want to stop resetting the IPU in the future, masking all interrupts before registering the irq handlers will not be enough to avoid spurious interrupts. We also have to clear them. Signed-off-by: Philipp Zabel Acked-by: Liu Ying

gpu: ipu-v3: add YUV 4:4:4 support

2016-10-20T12:40:10Z

The IDMAC does support reading and writing DRM_FORMAT_YUV444 and DRM_FORMAT_YVU444. Signed-off-by: Philipp Zabel Acked-by: Liu Ying