<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/plane.h, branch linux-5.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-05-31T12:30:11Z</updated>
<entry>
<title>drm/tegra: hub: Fix YUV support</title>
<updated>2021-05-31T12:30:11Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-05-27T18:15:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e16efff4e5f490ce34a8c60d9ae7297dca5eb616'/>
<id>urn:sha1:e16efff4e5f490ce34a8c60d9ae7297dca5eb616</id>
<content type='text'>
The driver currently exposes several YUV formats but fails to properly
program all the registers needed to display such formats. Add the right
programming sequences so that overlay windows can be used to accelerate
color format conversions in multimedia playback use-cases.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Support horizontal reflection</title>
<updated>2020-07-17T14:06:17Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-06-17T23:40:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cd740777d29d7053e0172c7e0105789428425941'/>
<id>urn:sha1:cd740777d29d7053e0172c7e0105789428425941</id>
<content type='text'>
Support horizontal reflection mode which will allow to support 180°
rotation mode when combined with the vertical reflection.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Rename bottom_up to reflect_y</title>
<updated>2020-07-17T14:06:16Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-06-17T23:40:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e9e476f7f7eaaf12058290f83cccbcb076596b2f'/>
<id>urn:sha1:e9e476f7f7eaaf12058290f83cccbcb076596b2f</id>
<content type='text'>
This makes the naming consistent with the DRM core.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Support DMA API for display controllers</title>
<updated>2019-10-29T14:04:36Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-10-28T12:37:17Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2e8d8749f6f9bb35b947228271dc9ec31be93335'/>
<id>urn:sha1:2e8d8749f6f9bb35b947228271dc9ec31be93335</id>
<content type='text'>
If a display controller is not attached to an explicit IOMMU domain,
which usually means that it's connected to an IOMMU domain controlled by
the DMA API, make sure to map the framebuffer to the display controller
address space. This allows us to transparently handle setups where the
display controller is attached to an IOMMU or setups where it isn't. It
also allows the driver to work with a DMA API that is backed by an
IOMMU.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500</title>
<updated>2019-06-19T15:09:55Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2019-06-04T08:11:33Z</published>
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<id>urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520</id>
<content type='text'>
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Support rotation property</title>
<updated>2018-05-18T19:56:21Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2018-03-19T16:20:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=995c5a509fb032ddd83eff4f3772c7fc8ff0b7ec'/>
<id>urn:sha1:995c5a509fb032ddd83eff4f3772c7fc8ff0b7ec</id>
<content type='text'>
Currently only the DRM_MODE_REFLECT_Y rotation is supported. The driver
already supports reflection on the Y axis via a custom flag which is not
very useful because it requires custom userspace. Add the standard
rotation property that supports 0 degree rotation and Y axis reflection
for primary and overlay planes to provide a better interface than the
custom flag.

v2: keep custom flag for ABI compatibility (Dmitry)

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Implement zpos plane property for older Tegras</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2018-05-04T14:39:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3dae08bc076b93487ed2df50bcfa892113e89d9d'/>
<id>urn:sha1:3dae08bc076b93487ed2df50bcfa892113e89d9d</id>
<content type='text'>
Older Tegra's do not support plane's Z position handling in hardware,
but the hardware provides knobs to implement it in software.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Implement legacy blending</title>
<updated>2017-12-21T13:55:55Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2017-12-20T08:39:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ebae8d07435ae91314f4a28d69b530d09c625815'/>
<id>urn:sha1:ebae8d07435ae91314f4a28d69b530d09c625815</id>
<content type='text'>
This implements alpha blending on legacy display controllers (Tegra20,
Tegra30 and Tegra114). While it's theoretically possible to support the
zpos property to enable userspace to specify the Z-order of each plane
individually, this is not currently supported and the same fixed Z-
order as previously defined is used.

Reverts commit 71835caa00e8 ("drm/tegra: fb: Force alpha formats") since
the opaque formats are now supported.

Reported-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Fixes: 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats")
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Implement zpos property</title>
<updated>2017-12-21T13:52:35Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2017-12-14T12:46:20Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ab7d3f5826c55ad23101327eab435660caa83436'/>
<id>urn:sha1:ab7d3f5826c55ad23101327eab435660caa83436</id>
<content type='text'>
Implement the standard zpos property for planes on Tegra124 and later.
Earlier generations have a different blending unit that needs different
programming.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Use direct offset to plane registers</title>
<updated>2017-12-21T13:52:34Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2017-12-14T12:37:53Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1087fac18b8e3ec8fadf1595bbc46dce7ff08a81'/>
<id>urn:sha1:1087fac18b8e3ec8fadf1595bbc46dce7ff08a81</id>
<content type='text'>
Traditionally, windows were accessed indirectly, through a register
selection window that required a global register to be programmed with
the index of the window to access. Since the global register could be
written from modesetting functions as well as the interrupt handler
concurrently, accesses had to be serialized using a lock. Using direct
accesses to the window registers the lock can be avoided.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
