<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/plane.c, branch linux-5.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-05-31T12:30:11Z</updated>
<entry>
<title>drm/tegra: hub: Fix YUV support</title>
<updated>2021-05-31T12:30:11Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-05-27T18:15:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e16efff4e5f490ce34a8c60d9ae7297dca5eb616'/>
<id>urn:sha1:e16efff4e5f490ce34a8c60d9ae7297dca5eb616</id>
<content type='text'>
The driver currently exposes several YUV formats but fails to properly
program all the registers needed to display such formats. Add the right
programming sequences so that overlay windows can be used to accelerate
color format conversions in multimedia playback use-cases.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Support sector layout on Tegra194</title>
<updated>2021-03-31T15:42:14Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-03-26T14:51:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7b6f846785f41d57917e36851c120cfbe87f0809'/>
<id>urn:sha1:7b6f846785f41d57917e36851c120cfbe87f0809</id>
<content type='text'>
Tegra194 has a special physical address bit that enables some memory
swizzling logic to support different sector layouts. Support the bit
that selects the sector layout which is passed in the framebuffer
modifier.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gem: Add a clarifying comment</title>
<updated>2021-03-31T15:42:14Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-03-26T14:51:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=476e93205ff61a6507bcba28f4f01269b65ebb38'/>
<id>urn:sha1:476e93205ff61a6507bcba28f4f01269b65ebb38</id>
<content type='text'>
Clarify when a fixed IOV address can be used and when a buffer has to
be mapped before the IOVA can be used.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/gem: Move drm_gem_fb_prepare_fb() to GEM atomic helpers</title>
<updated>2021-02-23T07:54:22Z</updated>
<author>
<name>Thomas Zimmermann</name>
</author>
<published>2021-02-22T14:17:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=820c1707177c6fe96beed7f8cc842a683afbf890'/>
<id>urn:sha1:820c1707177c6fe96beed7f8cc842a683afbf890</id>
<content type='text'>
The function drm_gem_fb_prepare_fb() is a helper for atomic modesetting,
but currently located next to framebuffer helpers. Move it to GEM atomic
helpers, rename it slightly and adopt the drivers. Same for the rsp
simple-pipe helper.

Compile-tested with x86-64, aarch64 and arm. The patch is fairly large,
but there are no functional changes.

v3:
	* remove out-comented line in drm_gem_framebuffer_helper.h
	  (Maxime)
v2:
	* rename to drm_gem_plane_helper_prepare_fb() (Daniel)
	* add tutorial-style documentation

Signed-off-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
Acked-by: Maxime Ripard &lt;mripard@kernel.org&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210222141756.7864-1-tzimmermann@suse.de
</content>
</entry>
<entry>
<title>drm: tegra: fix common struct sg_table related issues</title>
<updated>2020-09-10T06:18:35Z</updated>
<author>
<name>Marek Szyprowski</name>
</author>
<published>2020-04-28T11:10:10Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d4fea3e61b47a22e57a58d7afd6f0209051208bd'/>
<id>urn:sha1:d4fea3e61b47a22e57a58d7afd6f0209051208bd</id>
<content type='text'>
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
returns the number of the created entries in the DMA address space.
However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
dma_unmap_sg must be called with the original number of the entries
passed to the dma_map_sg().

struct sg_table is a common structure used for describing a non-contiguous
memory buffer, used commonly in the DRM and graphics subsystems. It
consists of a scatterlist with memory pages and DMA addresses (sgl entry),
as well as the number of scatterlist entries: CPU pages (orig_nents entry)
and DMA mapped pages (nents entry).

It turned out that it was a common mistake to misuse nents and orig_nents
entries, calling DMA-mapping functions with a wrong number of entries or
ignoring the number of mapped entries returned by the dma_map_sg()
function.

To avoid such issues, lets use a common dma-mapping wrappers operating
directly on the struct sg_table objects and use scatterlist page
iterators where possible. This, almost always, hides references to the
nents and orig_nents entries, making the code robust, easier to follow
and copy/paste safe.

Signed-off-by: Marek Szyprowski &lt;m.szyprowski@samsung.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Support horizontal reflection</title>
<updated>2020-07-17T14:06:17Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-06-17T23:40:39Z</published>
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<id>urn:sha1:cd740777d29d7053e0172c7e0105789428425941</id>
<content type='text'>
Support horizontal reflection mode which will allow to support 180°
rotation mode when combined with the vertical reflection.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Rename bottom_up to reflect_y</title>
<updated>2020-07-17T14:06:16Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-06-17T23:40:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e9e476f7f7eaaf12058290f83cccbcb076596b2f'/>
<id>urn:sha1:e9e476f7f7eaaf12058290f83cccbcb076596b2f</id>
<content type='text'>
This makes the naming consistent with the DRM core.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Reuse IOVA mapping where possible</title>
<updated>2020-02-06T17:21:55Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2020-02-04T13:59:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=273da5a046965ccf0ec79eb63f2d5173467e20fa'/>
<id>urn:sha1:273da5a046965ccf0ec79eb63f2d5173467e20fa</id>
<content type='text'>
This partially reverts the DMA API support that was recently merged
because it was causing performance regressions on older Tegra devices.
Unfortunately, the cache maintenance performed by dma_map_sg() and
dma_unmap_sg() causes performance to drop by a factor of 10.

The right solution for this would be to cache mappings for buffers per
consumer device, but that's a bit involved. Instead, we simply revert to
the old behaviour of sharing IOVA mappings when we know that devices can
do so (i.e. they share the same IOMMU domain).

Cc: &lt;stable@vger.kernel.org&gt; # v5.5
Reported-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gem: Remove premature import restrictions</title>
<updated>2019-12-04T12:36:23Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-12-03T16:19:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=49f821919bb9d45de7f1cde6072de01d36235b5d'/>
<id>urn:sha1:49f821919bb9d45de7f1cde6072de01d36235b5d</id>
<content type='text'>
All the display related blocks on Tegra require contiguous memory. Using
the DMA API, there is no knowing at import time which device will end up
using the buffer, so it's not known whether or not an IOMMU will be used
to map the buffer.

Move the check for non-contiguous buffers/mappings to the tegra_dc_pin()
function which is now the earliest point where it is known if a DMA BUF
can be used by the given device or not.

v2: add check for contiguous buffer/mapping in tegra_dc_pin()

Reviewed-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Support DMA API for display controllers</title>
<updated>2019-10-29T14:04:36Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-10-28T12:37:17Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2e8d8749f6f9bb35b947228271dc9ec31be93335'/>
<id>urn:sha1:2e8d8749f6f9bb35b947228271dc9ec31be93335</id>
<content type='text'>
If a display controller is not attached to an explicit IOMMU domain,
which usually means that it's connected to an IOMMU domain controlled by
the DMA API, make sure to map the framebuffer to the display controller
address space. This allows us to transparently handle setups where the
display controller is attached to an IOMMU or setups where it isn't. It
also allows the driver to work with a DMA API that is backed by an
IOMMU.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
