<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/dpaux.c, branch linux-4.6.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.6.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.6.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2015-12-14T09:50:37Z</updated>
<entry>
<title>drm/tegra: sor: Operate on struct drm_dp_aux *</title>
<updated>2015-12-14T09:50:37Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2015-07-08T11:39:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=9542c2376efaf5a6ae65b4aa0014e9f35ba36e17'/>
<id>urn:sha1:9542c2376efaf5a6ae65b4aa0014e9f35ba36e17</id>
<content type='text'>
Instead of getting a pointer to the driver-specific wrapper of AUX
channels, use the AUX channel objects directly to avoid hackish casting
between the two types.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Handle I2C_WRITE_STATUS_UPDATE for address only writes</title>
<updated>2015-09-08T18:15:42Z</updated>
<author>
<name>Ville Syrjälä</name>
</author>
<published>2015-08-27T14:23:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f993406182b3ffad7c53ffc180b65e2b7e3d8986'/>
<id>urn:sha1:f993406182b3ffad7c53ffc180b65e2b7e3d8986</id>
<content type='text'>
A address-only I2C_WRITE can't be replied with a short i2c ack, but I
suppose it could be replied with an i2c defer. So the code should be
prepared for an address-only I2C_WRITE_STATUS_UPDATE.

Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: "Terje Bergström" &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/dp: s/I2C_STATUS/I2C_WRITE_STATUS_UPDATE/</title>
<updated>2015-09-08T18:12:38Z</updated>
<author>
<name>Ville Syrjälä</name>
</author>
<published>2015-08-27T14:23:26Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2b712be72fddc74ac12c2857af24a20a93d9e9c0'/>
<id>urn:sha1:2b712be72fddc74ac12c2857af24a20a93d9e9c0</id>
<content type='text'>
Rename the I2C_STATUS request to I2C_WRITE_STATUS_UPDATE to match the
spec.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Disable interrupt when detached</title>
<updated>2015-08-13T11:47:49Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2015-07-03T12:56:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=9e532b3ad9a7fc5f00d29c766439ffbdcc403146'/>
<id>urn:sha1:9e532b3ad9a7fc5f00d29c766439ffbdcc403146</id>
<content type='text'>
When the DPAUX isn't attached to an SOR the interrupts are not useful.
This also prevents a race that could potentially cause a crash on driver
removal.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Configure pads as I2C by default</title>
<updated>2015-08-13T11:47:47Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2015-04-27T13:16:26Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3227166c3bd64dc3a44b7a1bf79efff34ec27aa3'/>
<id>urn:sha1:3227166c3bd64dc3a44b7a1bf79efff34ec27aa3</id>
<content type='text'>
The DPAUX code paths already configure the pads in AUX mode, but there
is no way to reconfigure them in I2C mode for HDMI (the DPAUX module is
unused in that case). Enabling the pads in I2C mode by default is the
quickest way to support HDMI. Eventually this may need an explicit call
in the user drivers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Provide error message in probe</title>
<updated>2015-08-13T11:47:46Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2015-04-27T12:50:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=08f580ef2fcef724db1107545bc14306b7c9eae2'/>
<id>urn:sha1:08f580ef2fcef724db1107545bc14306b7c9eae2</id>
<content type='text'>
When probing the dpaux device fails, output proper error messages to
help diagnose the cause of the failure.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Registers are 32-bit</title>
<updated>2015-06-12T14:26:04Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2015-06-02T11:13:01Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8a8005e3e19915559b542bf85cc1b17024ee1d31'/>
<id>urn:sha1:8a8005e3e19915559b542bf85cc1b17024ee1d31</id>
<content type='text'>
Use a sized unsigned 32-bit data type (u32) to store register contents.
The DPAUX registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Fix transfers larger than 4 bytes</title>
<updated>2015-06-12T14:22:46Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2015-06-11T16:33:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3c1dae0a07c651526f8e878d223a88f82caa5a50'/>
<id>urn:sha1:3c1dae0a07c651526f8e878d223a88f82caa5a50</id>
<content type='text'>
The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Renaming DP training vswing pre emph defines</title>
<updated>2014-09-03T09:05:41Z</updated>
<author>
<name>Sonika Jindal</name>
</author>
<published>2014-08-08T10:53:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=eeb82a5cdb9ab8c5690186b60b2a2bc551fbdf5c'/>
<id>urn:sha1:eeb82a5cdb9ab8c5690186b60b2a2bc551fbdf5c</id>
<content type='text'>
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 &lt;&lt; 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 &lt;&lt; 0)

...

Signed-off-by: Sonika Jindal &lt;sonika.jindal@intel.com&gt;
Acked-by: Dave Airlie &lt;airlied@gmail.com&gt;
Acked-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/tegra: add MODULE_DEVICE_TABLEs</title>
<updated>2014-08-04T08:07:39Z</updated>
<author>
<name>Stephen Warren</name>
</author>
<published>2014-06-18T22:21:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ef70728c7a6571a1a7115031e932b811f1740b2e'/>
<id>urn:sha1:ef70728c7a6571a1a7115031e932b811f1740b2e</id>
<content type='text'>
When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow
the module to be auto-loaded since the module will match the devices
instantiated from device tree.

(Notes for stable: in 3.14+, just git rm any conflicting file, since they
are added in later kernels. For 3.13 and below, manual merging will be
needed)

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
