<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/dc.h, branch linux-5.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.14.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-05-31T12:30:11Z</updated>
<entry>
<title>drm/tegra: hub: Implement basic scaling support</title>
<updated>2021-05-31T12:30:11Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-05-27T18:27:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ecc583e22d4689e38a528a8bf841ba1ce58edd7b'/>
<id>urn:sha1:ecc583e22d4689e38a528a8bf841ba1ce58edd7b</id>
<content type='text'>
Parameterize code in several places to allow scaling of windows. Note
that this currently still relies on static programming of the various
metering and memory pool allocation registers. This seems to work for
the common cases, but may eventually need to be updated to support
use-cases with multiple windows and higher bandwidth and latency
requirements.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: hub: Fix YUV support</title>
<updated>2021-05-31T12:30:11Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-05-27T18:15:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e16efff4e5f490ce34a8c60d9ae7297dca5eb616'/>
<id>urn:sha1:e16efff4e5f490ce34a8c60d9ae7297dca5eb616</id>
<content type='text'>
The driver currently exposes several YUV formats but fails to properly
program all the registers needed to display such formats. Add the right
programming sequences so that overlay windows can be used to accelerate
color format conversions in multimedia playback use-cases.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Support sector layout on Tegra194</title>
<updated>2021-03-31T15:42:14Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-03-26T14:51:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7b6f846785f41d57917e36851c120cfbe87f0809'/>
<id>urn:sha1:7b6f846785f41d57917e36851c120cfbe87f0809</id>
<content type='text'>
Tegra194 has a special physical address bit that enables some memory
swizzling logic to support different sector layouts. Support the bit
that selects the sector layout which is passed in the framebuffer
modifier.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Implement hardware cursor on Tegra186 and later</title>
<updated>2021-03-31T15:42:14Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2021-03-26T14:51:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d5ec699db5bb15f981f1632d058ffe857d649765'/>
<id>urn:sha1:d5ec699db5bb15f981f1632d058ffe857d649765</id>
<content type='text'>
The hardware cursor on Tegra186 differs slightly from the implementation
on older SoC generations. In particular the new implementation relies on
software for clipping the cursor against the screen. Fortunately, atomic
KMS already computes clipped coordinates for (cursor) planes, so this is
trivial to implement.

The format supported by the hardware cursor is also slightly different.

v2: use more drm_rect helpers (Dmitry)

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Support horizontal reflection</title>
<updated>2020-07-17T14:06:17Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-06-17T23:40:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cd740777d29d7053e0172c7e0105789428425941'/>
<id>urn:sha1:cd740777d29d7053e0172c7e0105789428425941</id>
<content type='text'>
Support horizontal reflection mode which will allow to support 180°
rotation mode when combined with the vertical reflection.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Rename bottom_up to reflect_y</title>
<updated>2020-07-17T14:06:16Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-06-17T23:40:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e9e476f7f7eaaf12058290f83cccbcb076596b2f'/>
<id>urn:sha1:e9e476f7f7eaaf12058290f83cccbcb076596b2f</id>
<content type='text'>
This makes the naming consistent with the DRM core.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Move IOMMU group into host1x client</title>
<updated>2019-10-28T10:18:37Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-02-08T13:35:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=aacdf19849734d1be5e407932228ae101ba5b92f'/>
<id>urn:sha1:aacdf19849734d1be5e407932228ae101ba5b92f</id>
<content type='text'>
Handling of the IOMMU group attachment is common to all clients, so move
the group into the client to simplify code.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500</title>
<updated>2019-06-19T15:09:55Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2019-06-04T08:11:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d2912cb15bdda8ba4a5dd73396ad62641af2f520'/>
<id>urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520</id>
<content type='text'>
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Add Tegra194 support</title>
<updated>2018-09-26T14:04:39Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2018-09-21T10:27:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=474431968507d437d340de35b709aa3b41f8c996'/>
<id>urn:sha1:474431968507d437d340de35b709aa3b41f8c996</id>
<content type='text'>
The display controllers found on Tegra194 are almost identical to those
found on Tegra186.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Rename supports_blending to has_legacy_blending</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2018-05-04T14:40:00Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a43d0a00ea58a665905d94e8ab469ff888b1b0e1'/>
<id>urn:sha1:a43d0a00ea58a665905d94e8ab469ff888b1b0e1</id>
<content type='text'>
Older Tegra chips do support blending as well. Rename the SoC info entry
.supports_blending to .has_legacy_blending to eliminate the confusion.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
