Hosts the 0x221E linux distro kernel. https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.15.y 2014-04-04T07:12:50Z 2014-04-04T07:12:50Z Thierry Reding 2013-11-15T15:06:05Z urn:sha1:6b6b604215c64666fbf0fed939a5c312cc7b12fe Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-12-20T14:56:07Z Thierry Reding 2013-12-12T10:06:55Z urn:sha1:72d302861530bcdb780ea57ebfc3dff6ec4f802c Some of the code in the CRTC's mode setting code is specific to the RGB output or needs to be called slightly differently depending on the type of output. Push that code down into the output drivers. Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-12-20T14:56:06Z Thierry Reding 2013-12-12T10:03:59Z urn:sha1:8620fc629aeec02ac3b3735703940696386a3039 Tegra124 and later support interlacing, but the driver doesn't support it yet. Make sure interlacing stays disabled on hardware that supports it. Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-12-20T14:56:04Z Thierry Reding 2013-09-03T06:45:46Z urn:sha1:dec727399a4b36bec87b7b4d4c1b20025e69758a This commit adds support for both DSI outputs found on Tegra. Only very minimal functionality is implemented, so advanced features like ganged mode won't work. Due to the lack of other test hardware, some sections of the driver are hardcoded to work with Dalmore. Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-10-31T08:55:46Z Thierry Reding 2013-10-07T07:47:58Z urn:sha1:db7fbdfd25ee009165b6c3b80a9d1c6d8534ad94 The gr3d engine renders images bottom-up. Allow buffers that are used for 3D content to be marked as such and implement support in the display controller to present them properly. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-10-31T08:55:46Z Thierry Reding 2013-10-04T20:34:01Z urn:sha1:773af77fc479fd454c3f6836f86bf63996545cf4 The gr2d and gr3d engines work more efficiently on buffers with a tiled memory layout. Allow created buffers to be marked as tiled so that the display controller can scan them out properly. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-10-31T08:55:40Z Thierry Reding 2013-10-09T08:32:49Z urn:sha1:dee8268f8fb218c9e9b604a40f7dbdd395e910f9 In order to make subsystem-wide changes easier, move the Tegra DRM driver back into the DRM tree. Signed-off-by: Thierry Reding <treding@nvidia.com> 2013-04-22T10:39:11Z Terje Bergstrom 2013-03-22T14:34:05Z urn:sha1:4231c6b01af9f0f3eeca4b8d0d87125d78233b41 Make drm part of host1x driver. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> 2013-02-22T07:21:27Z Thierry Reding 2012-11-28T11:00:18Z urn:sha1:3c03c46ac80ea7edc3b8f2ba85085de54aec15cd All the necessary support bits like .mode_set_base() and VBLANK are now available, so page-flipping case easily be implemented on top. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> 2013-02-22T07:21:12Z Thierry Reding 2012-11-04T20:47:13Z urn:sha1:f34bc78741815d0ad07298a42101a1ee2e2bcdd2 Add support for the B and C planes which support RGB and YUV pixel formats and can be used as overlays or hardware cursor. Currently 32-bit XRGB as well as UYVY, YUV420 and YUV422 pixel formats are advertised. Other formats should be easy to add but these are the most common ones and should cover the majority of use-cases. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>