<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/dc.c, branch linux-4.19.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2023-01-18T10:30:13Z</updated>
<entry>
<title>drm/tegra: Add missing clk_disable_unprepare() in tegra_dc_probe()</title>
<updated>2023-01-18T10:30:13Z</updated>
<author>
<name>Zhang Zekun</name>
</author>
<published>2022-08-02T08:50:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=00e875d200342cc4441ff66470fe14ef29b66e84'/>
<id>urn:sha1:00e875d200342cc4441ff66470fe14ef29b66e84</id>
<content type='text'>
[ Upstream commit 7ad4384d53c67672a8720cdc2ef638d7d1710ab8 ]

Add the missing clk_disable_unprepare() before return from
tegra_dc_probe() in the error handling path.

Fixes: f68ba6912bd2 ("drm/tegra: dc: Link DC1 to DC0 on Tegra20")
Signed-off-by: Zhang Zekun &lt;zhangzekun11@huawei.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Don't set PLL clock to 0Hz</title>
<updated>2021-04-16T09:49:30Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2021-03-02T13:15:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=41ed08a9f69534914977520b601f6b1551841ad8'/>
<id>urn:sha1:41ed08a9f69534914977520b601f6b1551841ad8</id>
<content type='text'>
[ Upstream commit f8fb97c915954fc6de6513cdf277103b5c6df7b3 ]

RGB output doesn't allow to change parent clock rate of the display and
PCLK rate is set to 0Hz in this case. The tegra_dc_commit_state() shall
not set the display clock to 0Hz since this change propagates to the
parent clock. The DISP clock is defined as a NODIV clock by the tegra-clk
driver and all NODIV clocks use the CLK_SET_RATE_PARENT flag.

This bug stayed unnoticed because by default PLLP is used as the parent
clock for the display controller and PLLP silently skips the erroneous 0Hz
rate changes because it always has active child clocks that don't permit
rate changes. The PLLP isn't acceptable for some devices that we want to
upstream (like Samsung Galaxy Tab and ASUS TF700T) due to a display panel
clock rate requirements that can't be fulfilled by using PLLP and then the
bug pops up in this case since parent clock is set to 0Hz, killing the
display output.

Don't touch DC clock if pclk=0 in order to fix the problem.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>driver core: Rename flag AUTOREMOVE to AUTOREMOVE_CONSUMER</title>
<updated>2018-07-09T10:14:31Z</updated>
<author>
<name>Vivek Gautam</name>
</author>
<published>2018-06-27T12:50:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e88728f46cfbb59cc7e7acf1d230c05ec093764e'/>
<id>urn:sha1:e88728f46cfbb59cc7e7acf1d230c05ec093764e</id>
<content type='text'>
Now that we want to add another flag to autoremove the device link
on supplier unbind, it's fair to rename the existing flag from
DL_FLAG_AUTOREMOVE to DL_FLAG_AUTOREMOVE_CONSUMER so that we can
add similar flag for supplier later.
And, while we are touching device.h, fix a doc build warning.

Signed-off-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Support rotation property</title>
<updated>2018-05-18T19:56:21Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2018-03-19T16:20:46Z</published>
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<id>urn:sha1:995c5a509fb032ddd83eff4f3772c7fc8ff0b7ec</id>
<content type='text'>
Currently only the DRM_MODE_REFLECT_Y rotation is supported. The driver
already supports reflection on the Y axis via a custom flag which is not
very useful because it requires custom userspace. Add the standard
rotation property that supports 0 degree rotation and Y axis reflection
for primary and overlay planes to provide a better interface than the
custom flag.

v2: keep custom flag for ABI compatibility (Dmitry)

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Rename supports_blending to has_legacy_blending</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2018-05-04T14:40:00Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a43d0a00ea58a665905d94e8ab469ff888b1b0e1'/>
<id>urn:sha1:a43d0a00ea58a665905d94e8ab469ff888b1b0e1</id>
<content type='text'>
Older Tegra chips do support blending as well. Rename the SoC info entry
.supports_blending to .has_legacy_blending to eliminate the confusion.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Implement zpos plane property for older Tegras</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2018-05-04T14:39:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3dae08bc076b93487ed2df50bcfa892113e89d9d'/>
<id>urn:sha1:3dae08bc076b93487ed2df50bcfa892113e89d9d</id>
<content type='text'>
Older Tegra's do not support plane's Z position handling in hardware,
but the hardware provides knobs to implement it in software.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Enable plane scaling filters</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2018-05-04T14:39:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=acc6a3a9afdd4e0537342012656cdb5c4a3127c5'/>
<id>urn:sha1:acc6a3a9afdd4e0537342012656cdb5c4a3127c5</id>
<content type='text'>
Currently resized plane produces a "pixelated" image which doesn't look
nice, especially in a case of a video overlay. Enable scaling filters that
significantly improve image quality of a scaled overlay.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Refactor IOMMU attach/detach</title>
<updated>2018-05-17T12:08:40Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2018-05-04T13:02:24Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=0c407de5ed1a329468122cbf4f3e727e0c1e3f36'/>
<id>urn:sha1:0c407de5ed1a329468122cbf4f3e727e0c1e3f36</id>
<content type='text'>
Attaching to and detaching from an IOMMU uses the same code sequence in
every driver, so factor it out into separate helpers.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Free syncpoint on errors</title>
<updated>2018-05-04T15:07:06Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2018-05-04T13:00:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fd5ec0dc34dafa6c5bb46770ca283ae90a4db3c7'/>
<id>urn:sha1:fd5ec0dc34dafa6c5bb46770ca283ae90a4db3c7</id>
<content type='text'>
If an error happens during display controller initialization, the host1x
syncpoint previously requested would be leaked. Properly clean up the
syncpoint along with the other resources.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Balance IOMMU group refcounting</title>
<updated>2018-05-04T12:19:14Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2018-05-03T23:47:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6f75b16b2683eb7c86ce2c8d150bf3fa759103b9'/>
<id>urn:sha1:6f75b16b2683eb7c86ce2c8d150bf3fa759103b9</id>
<content type='text'>
Remove unneeded iommu_group_get() and add missing iommu_group_put(),
correcting IOMMU group refcount. This is a minor correction / cleanup that
doesn't really fix anything because Tegra's IOMMU driver are built-in and
hence groups refcounting can't hold IOMMU driver from unloading.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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