kernel.git/drivers/gpu/drm/tegra/dc.c, branch linux-3.8.y

Revert "drm: tegra: protect DC register access with mutex"

2012-12-30T11:58:20Z

This reverts commit 83c0bcb694be31dcd6c04bdd935b96a95a0af548. Lucas pointed out this was a mistake, and I missed the discussion, so just revert it out to save a rebase. Signed-off-by: Dave Airlie

drm: tegra: program only one window during modeset

2012-12-30T04:01:35Z

The intention is to program exactly WIN_A, not WIN_A and possibly others. Signed-off-by: Lucas Stach Signed-off-by: Dave Airlie

drm: tegra: protect DC register access with mutex

2012-12-30T04:01:33Z

Window properties are programmed through a shared aperture and have to happen atomically. Also we do the read-update-write dance on some of the shared regs. To make sure that different functions don't stumble over each other protect the register access with a mutex. Signed-off-by: Lucas Stach Signed-off-by: Dave Airlie

drm: tegra: fix front_porch <-> back_porch mixup

2012-12-30T04:01:31Z

Fixes wrong picture offset observed when using HDMI output with a Technisat HD TV. Signed-off-by: Lucas Stach Acked-by: Mark Zhang Tested-by: Mark Zhang Signed-off-by: Dave Airlie

drm: tegra: Add Tegra30 support

2012-11-28T10:07:02Z

Add support for host1x, the display controllers and HDMI on the Tegra30 SoC. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Tested-by: Mark Zhang Signed-off-by: Dave Airlie

drm: tegra: Use framebuffer pitch as line stride

2012-11-28T10:05:46Z

Instead of using the stride derived from the display mode, use the pitch associated with the currently active framebuffer. This fixes a bug where the LCD display content would be skewed when enabling HDMI with a video mode different from that of the LCD. Signed-off-by: Thierry Reding Tested-by: Terje Bergstrom Tested-by: Mark Zhang Tested-by: Stephen Warren Signed-off-by: Dave Airlie

drm: Add NVIDIA Tegra20 support

2012-11-20T05:43:41Z

This commit adds a KMS driver for the Tegra20 SoC. This includes basic support for host1x and the two display controllers found on the Tegra20 SoC. Each display controller can drive a separate RGB/LVDS output. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Acked-by: Mark Zhang Reviewed-by: Mark Zhang Tested-by: Mark Zhang Tested-and-acked-by: Alexandre Courbot Acked-by: Terje Bergstrom Tested-by: Terje Bergstrom Signed-off-by: Dave Airlie