<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/dc.c, branch linux-3.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.17.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.17.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2014-08-04T08:07:39Z</updated>
<entry>
<title>drm/tegra: add MODULE_DEVICE_TABLEs</title>
<updated>2014-08-04T08:07:39Z</updated>
<author>
<name>Stephen Warren</name>
</author>
<published>2014-06-18T22:21:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ef70728c7a6571a1a7115031e932b811f1740b2e'/>
<id>urn:sha1:ef70728c7a6571a1a7115031e932b811f1740b2e</id>
<content type='text'>
When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow
the module to be auto-loaded since the module will match the devices
instantiated from device tree.

(Notes for stable: in 3.14+, just git rm any conflicting file, since they
are added in later kernels. For 3.13 and below, manual merging will be
needed)

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc - Reset controller on driver remove</title>
<updated>2014-08-04T08:07:38Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-07-11T06:39:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5482d75a6597de97f79255a257c486a6960c6c65'/>
<id>urn:sha1:5482d75a6597de97f79255a257c486a6960c6c65</id>
<content type='text'>
Since the device will no longer be used, may as well keep it in reset to
potentially save some power and make sure it is in a clean state the
next time it's probed.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Properly align stride for framebuffers</title>
<updated>2014-08-04T08:07:38Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-07-11T06:29:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d1f3e1e0b38d49cbb996dcf0fde5b5205d12a23d'/>
<id>urn:sha1:d1f3e1e0b38d49cbb996dcf0fde5b5205d12a23d</id>
<content type='text'>
Tegra20 and Tegra30 both required the buffer line stride to be aligned
on 8 byte boundaries. Tegra114 and Tegra124 increased the alignment to
64 bytes. Introduce a parameter to specify the alignment requirements
for each display controller and round up the pitch of newly allocated
framebuffers appropriately.

Originally-by: Stéphane Marchesin &lt;marcheu@chromium.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Implement more tiling modes</title>
<updated>2014-08-04T08:07:34Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-06-03T12:48:12Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8'/>
<id>urn:sha1:c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8</id>
<content type='text'>
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.

Tested-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add hardware cursor support</title>
<updated>2014-06-05T21:14:47Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-12-20T12:58:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e687651bc1ed96b0ad2ee9464f341c53563b5353'/>
<id>urn:sha1:e687651bc1ed96b0ad2ee9464f341c53563b5353</id>
<content type='text'>
Enable hardware cursor support on Tegra124. Earlier generations support
the hardware cursor to some degree as well, but not in a way that can be
generically exposed.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Remove host1x drm_bus implementation</title>
<updated>2014-06-05T21:14:46Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-05-22T07:57:15Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=9910f5c455de10f0eb2559093a7adad65f6c05cd'/>
<id>urn:sha1:9910f5c455de10f0eb2559093a7adad65f6c05cd</id>
<content type='text'>
The DRM core can now cope with drivers that don't have an associated
struct drm_bus, so the host1x implementation is no longer useful.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc - Compute shift clock divider in output drivers</title>
<updated>2014-06-05T21:09:33Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-03-26T12:32:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=91eded9b481e61913d98142927b559af33a180a7'/>
<id>urn:sha1:91eded9b481e61913d98142927b559af33a180a7</id>
<content type='text'>
The shift clock divider is highly dependent on the type of output, so
push computation of it down into the output drivers. The old code used
to work merely by accident.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc - Move around shift clock programming</title>
<updated>2014-06-05T21:09:32Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-03-26T11:32:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=dbb3f2f751069bc757fbdbe8911a7e784e850b24'/>
<id>urn:sha1:dbb3f2f751069bc757fbdbe8911a7e784e850b24</id>
<content type='text'>
Program the shift clock divider in tegra_crtc_setup_clk() since that's
where the divider is computed, so passing it around can be avoided.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc - Use proper H/V ref-to-sync values</title>
<updated>2014-06-05T21:09:20Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-04-16T07:22:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=0444c0ff3cef9f99b19bbb1f0b3f5d7a22daab25'/>
<id>urn:sha1:0444c0ff3cef9f99b19bbb1f0b3f5d7a22daab25</id>
<content type='text'>
For HDMI compliance both of these values need to be set to 1.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc - Do not touch power control register</title>
<updated>2014-06-05T21:09:19Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-04-16T07:52:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=501bcbd1b233edc160d0c770c03747a1c4aa14e5'/>
<id>urn:sha1:501bcbd1b233edc160d0c770c03747a1c4aa14e5</id>
<content type='text'>
Setting the bits in this register is dependent on the output type driven
by the display controller. All output drivers already set these properly
so there is no need to do it here again.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
