<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/tegra/dc.c, branch linux-3.15.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.15.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.15.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2014-04-24T13:04:30Z</updated>
<entry>
<title>drm/tegra: restrict plane loops to legacy planes</title>
<updated>2014-04-24T13:04:30Z</updated>
<author>
<name>Daniel Vetter</name>
</author>
<published>2014-04-23T13:15:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2b4c36612efac173397756398000921a7771fdda'/>
<id>urn:sha1:2b4c36612efac173397756398000921a7771fdda</id>
<content type='text'>
In Matt Ropers primary plane series a set of prep patches like

commit af2b653bfb4ef40931b4d101ca842ce0c5da57ef
Author: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Date:   Tue Apr 1 15:22:32 2014 -0700

    drm/i915: Restrict plane loops to only operate on overlay planes (v2)

ensured that all exisiting users of the mode_config-&gt;plane_list
wouldn't change behaviour. Unfortunately tegra seems to have fallen
through the cracks. Fix it.

This regression was introduced in

commit e13161af80c185ecd8dc4641d0f5df58f9e3e0af
Author: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Date:   Tue Apr 1 15:22:38 2014 -0700

    drm: Add drm_crtc_init_with_planes() (v2)

The result was that we've unref'ed the fb for the primary plane twice,
leading to a use-after free bug. This is because the drm core will
already set crtc-&gt;primary-&gt;fb to NULL and do the unref for us, and the
crtc disable hook is called by the drm crtc helpers for exactly this
case.

Aside: Now that the fbdev helpers clean up planes there's no longer a
need to do this in drivers. So this could probably be nuked entirely
in linux-next.

Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm: Replace crtc fb with primary plane fb (v3)</title>
<updated>2014-04-02T00:18:28Z</updated>
<author>
<name>Matt Roper</name>
</author>
<published>2014-04-01T22:22:40Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f4510a2752b75ad5847b7935b68c233cab497f97'/>
<id>urn:sha1:f4510a2752b75ad5847b7935b68c233cab497f97</id>
<content type='text'>
Now that CRTC's have a primary plane, there's no need to track the
framebuffer in the CRTC.  Replace all references to the CRTC fb with the
primary plane's fb.

This patch was generated by the Coccinelle semantic patching tool using
the following rules:

        @@ struct drm_crtc C; @@
        -   (C).fb
        +   C.primary-&gt;fb

        @@ struct drm_crtc *C; @@
        -   (C)-&gt;fb
        +   C-&gt;primary-&gt;fb

v3: Generate patch via coccinelle.  Actual removal of crtc-&gt;fb has been
    moved to a subsequent patch.

v2: Fixup several lingering crtc-&gt;fb instances that were missed in the
    first patch iteration.  [Rob Clark]

Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Obtain head number from DT</title>
<updated>2014-01-23T14:51:32Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2014-01-09T16:08:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=13411ddd319057ae334a4084ebcf2c741b317f34'/>
<id>urn:sha1:13411ddd319057ae334a4084ebcf2c741b317f34</id>
<content type='text'>
The head number of a given display controller is fixed in hardware and
required to program outputs appropriately. Relying on the driver probe
order to determine this number will not work, since that could yield a
situation where the second head was probed first and would be assigned
head number 0 instead of 1.

By explicitly specifying the head number in the device tree, it is no
longer necessary to rely on these assumptions. As a fallback, if the
property isn't available, derive the head number from the display
controller node's position in the device tree. That's somewhat more
reliable than the previous default but not a proper solution.

Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Relocate some output-specific code</title>
<updated>2013-12-20T14:56:07Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-12-12T10:06:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=72d302861530bcdb780ea57ebfc3dff6ec4f802c'/>
<id>urn:sha1:72d302861530bcdb780ea57ebfc3dff6ec4f802c</id>
<content type='text'>
Some of the code in the CRTC's mode setting code is specific to the RGB
output or needs to be called slightly differently depending on the type
of output. Push that code down into the output drivers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add Tegra124 DC support</title>
<updated>2013-12-20T14:56:06Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-12-12T10:03:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8620fc629aeec02ac3b3735703940696386a3039'/>
<id>urn:sha1:8620fc629aeec02ac3b3735703940696386a3039</id>
<content type='text'>
Tegra124 and later support interlacing, but the driver doesn't support
it yet. Make sure interlacing stays disabled on hardware that supports
it.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: use reset framework</title>
<updated>2013-12-11T23:43:04Z</updated>
<author>
<name>Stephen Warren</name>
</author>
<published>2013-11-06T23:20:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ca48080a039f667c9a1e2d6236ea18dde2d36e7e'/>
<id>urn:sha1:ca48080a039f667c9a1e2d6236ea18dde2d36e7e</id>
<content type='text'>
Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Support bottom-up buffer objects</title>
<updated>2013-10-31T08:55:46Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-10-07T07:47:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=db7fbdfd25ee009165b6c3b80a9d1c6d8534ad94'/>
<id>urn:sha1:db7fbdfd25ee009165b6c3b80a9d1c6d8534ad94</id>
<content type='text'>
The gr3d engine renders images bottom-up. Allow buffers that are used
for 3D content to be marked as such and implement support in the display
controller to present them properly.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add support for tiled buffer objects</title>
<updated>2013-10-31T08:55:46Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-10-04T20:34:01Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=773af77fc479fd454c3f6836f86bf63996545cf4'/>
<id>urn:sha1:773af77fc479fd454c3f6836f86bf63996545cf4</id>
<content type='text'>
The gr2d and gr3d engines work more efficiently on buffers with a tiled
memory layout. Allow created buffers to be marked as tiled so that the
display controller can scan them out properly.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Allocate resources at probe time</title>
<updated>2013-10-31T08:55:41Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-10-14T12:26:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=59d29c0ec93fe9879673b302a182fb3fb80896c3'/>
<id>urn:sha1:59d29c0ec93fe9879673b302a182fb3fb80896c3</id>
<content type='text'>
Since the .init() and .exit() functions are executed whenever the DRM
driver is loaded or unloaded, care must be taken not to use them for
resource allocation. Otherwise deferred probing cannot be used, since
the .init() and .exit() are not run at probe time. Similarly the code
that frees resources must be run at .remove() time. If it is run from
the .exit() function, it can release resources multiple times.

To handle this more consistently, rename the tegra_output_parse_dt()
function to tegra_output_probe() and introduce tegra_output_remove()
which can be used to free output-related resources.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Properly cleanup and zero out resources</title>
<updated>2013-10-31T08:55:40Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2013-10-14T12:06:02Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f002abc19acb6f7cdb3d320f3b6f1a565c0be63e'/>
<id>urn:sha1:f002abc19acb6f7cdb3d320f3b6f1a565c0be63e</id>
<content type='text'>
When the DRM driver is unloaded, all the associated resources must be
cleaned up and zeroed out. This is necessary because of the architecture
of the Tegra DRM driver, where not all subdrivers are unloaded along
with the DRM driver. Therefore device-managed managed won't be freed and
memory cannot be assumed to have been cleared (because it hasn't been
reallocated using kzalloc()) by the time the DRM driver is reloaded. It
is therefore necessary to zero out the structures to prevent strange
errors (such as slab corruptions) from occurring.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
