kernel.git/drivers/gpu/drm/msm/registers, branch linux-rolling-stable

drm/msm/adreno: Introduce A8x GPU Support

2025-11-18T17:04:01Z

A8x is the next generation of Adreno GPUs, featuring a significant hardware design change. A major update to the design is the introduction of Slice architecture. Slices are sort of mini-GPUs within the GPU which are more independent in processing Graphics and compute workloads. Also, in addition to the BV and BR pipe we saw in A7x, CP has more concurrency with additional pipes. From a software interface perspective, these changes have a significant impact on the KMD side. First, the GPU register space has been extensively reorganized. Second, to avoid a register space explosion caused by the new slice architecture and additional pipes, many registers are now virtualized, instead of duplicated as in A7x. KMD must configure an aperture register with the appropriate slice and pipe ID before accessing these virtualized registers. Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689019/ Message-ID: <20251118-kaana-gpu-support-v4-14-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark

drm/msm/a8xx: Add support for A8x GMU

2025-11-18T17:04:00Z

A8x GMU configurations are very similar to A7x. Unfortunately, there are minor shuffling in the register offsets in the GMU CX register region. So, update the driver to use the correct register offsets on A8x hw. Some A8x GPUs have more than 16 powerlevels on GX domain and 4 on CX domain. To accommodate this, increase the arrays' sizes which hold gx and cx power levels. Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689013/ Message-ID: <20251118-kaana-gpu-support-v4-11-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark

drm/msm/a6xx: Rebase GMU register offsets

2025-11-18T17:04:00Z

GMU registers are always at a fixed offset from the GPU base address, a consistency maintained at least within a given architecture generation. In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689010/ Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark

drm/msm/a6xx: Sync latest register definitions

2025-11-18T17:04:00Z

Sync the latest register definitions from Mesa which includes the updates for A8x family. Co-developed-by: Rob Clark Signed-off-by: Rob Clark Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689009/ Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com>

drm/msm/adreno: Common-ize PIPE definitions

2025-11-18T15:31:59Z

Newer gen's introduce pipe enums which do not exist on older gens, but the numeric values do not conflict. IOW, they are backward compatible. So move its definition to adreno_common.xml. Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689001/ Message-ID: <20251118-kaana-gpu-support-v4-5-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark

drm/msm/registers: Fix encoding fields in 64b registers

2025-11-18T15:31:59Z

Based on mesa commit 3f70b0578402 ("freedreno/registers: Fix encoding fields in 64b registers"), but with some fixes to not skip emitting interrupt enum values. v2: Don't append "ull" to 32b reg MASK defines, to avoid printf format conversion warnings all over the place Co-developed-by: Connor Abbott Signed-off-by: Connor Abbott Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/689141/ Message-ID: <20251118152952.226510-1-robin.clark@oss.qualcomm.com>

drm/msm/registers: Sync GPU registers from mesa

2025-09-10T21:48:12Z

In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to fix a7xx GPU snapshot. Sync from mesa commit 15ee3873aa4d ("freedreno/registers: Update GMU register xml"). Cc: Karmjit Mahil Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/673558/

drm/msm/registers: Generate _HI/LO builders for reg64

2025-09-10T21:48:12Z

The upstream mesa copy of the GPU regs has shifted more things to reg64 instead of seperate 32b HI/LO reg32's. This works better with the "new- style" c++ builders that mesa has been migrating to for a6xx+ (to better handle register shuffling between gens), but it leaves the C builders with missing _HI/LO builders. So handle the special case of reg64, automatically generating the missing _HI/LO builders. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/673559/

drm/msm/registers: Make TPL1_BICUBIC_WEIGHTS_TABLE an array

2025-09-10T21:48:12Z

Synced from mesa commit 77c42c1a5752 ("freedreno/registers: Make TPL1_BICUBIC_WEIGHTS_TABLE an array"). Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/673552/

drm/msm/registers: Sync gen_header.py from mesa

2025-09-10T21:48:12Z

Sync from mesa commit 04e2140d8be7 ("freedreno/registers: remove python 3.9 dependency for compiling msm"). Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/673556/