kernel.git/drivers/gpu/drm/msm/msm_gpu.h, branch linux-4.10.y

drm/msm: gpu: Add A5XX target support

2016-11-28T20:14:15Z

Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark

drm/msm: Remove 'src_clk' from adreno configuration

2016-11-28T20:14:13Z

The adreno code inherited a silly workaround from downstream from the bad old days before decent clock control. grp_clk[0] (named 'src_clk') doesn't actually exist - it was used as a proxy for whatever the core clock actually was (usually 'core_clk'). All targets should be able to correctly request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark

drm/msm: gpu Add new gpu register read/write functions

2016-11-28T20:14:12Z

Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark

drm/msm: gpu: Return error on hw_init failure

2016-11-28T20:14:11Z

When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark

drm/msm: convert iova to 64b

2016-11-28T20:14:08Z

For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: Rob Clark

drm/msm: support multiple address spaces

2016-11-27T16:23:09Z

We can have various combinations of 64b and 32b address space, ie. 64b CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So best to decouple the device iova's from mmap offset. Signed-off-by: Rob Clark

drm/msm: move fence allocation out of msm_gpu_submit()

2016-09-15T21:43:51Z

Prep work for next patch. Signed-off-by: Rob Clark

drm/msm: drop return from gpu->submit()

2016-05-08T14:22:18Z

At this point, there is nothing left to fail. And submit already has a fence assigned and is added to the submit_list. Any problems from here on out are asynchronous (ie. hangcheck/recovery). Signed-off-by: Rob Clark

drm/msm: introduce msm_fence_context

2016-05-08T14:19:51Z

Better encapsulate the per-timeline stuff into fence-context. For now there is just a single fence-context, but eventually we'll also have one per-CRTC to enable fully explicit fencing. Signed-off-by: Rob Clark

drm/msm: restart queued submits after hang

2015-06-11T17:11:06Z

Track the list of in-flight submits. If the gpu hangs, retire up to an including the offending submit, and then re-submit the remainder. This way, for concurrently running piglit tests (for example), one failing test doesn't cause unrelated tests to fail simply because it's submit was queued up after one that triggered a hang. Signed-off-by: Rob Clark