kernel.git/drivers/gpu/drm/msm/dsi, branch linux-4.20.y

drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver

2019-02-12T19:02:18Z

[ Upstream commit c1866d44d149a1ea5c303632114fb6aa08cfd263 ] Fix the dsi clock names in the DSI 10nm PLL driver to match the names in the dispcc driver as those are according to the clock plan of the chipset. Changes in v2: - Update the clock diagram with the new clock name Reviewed-by: Sean Paul Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark Signed-off-by: Sasha Levin

drm/msm/dsi: configure VCO rate for 10nm PLL driver

2018-11-30T16:57:53Z

Currenty the VCO rate in the 10nm PLL driver relies on the parent rate which is not configured. Configure the VCO rate to 19.2 Mhz as required by the 10nm PLL driver. Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm: Don't fail bind if nothing connected to dsi

2018-10-04T00:24:50Z

If there is no bridge or panel connected to a dsi node, don't fail the entire msm bind. Just ignore the dsi block and move on. Cc: Doug Anderson Reviewed-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm: dsi: Return errors whan dt parsing fails

2018-10-04T00:24:49Z

If dt parsing fails, we should return an error instead of pretending everything completed successfully. Cc: Doug Anderson Reviewed-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm: dsi: Initialize msm_dsi->id to -1

2018-10-04T00:24:49Z

Currently msm_dsi->id is initialized to 0 during kzalloc. If bind fails for a secondary dsi device before its id can be properly set (such as during dt parsing), the id will point to the primary dsi device, causing its reference to be removed from dsi_manager's global (msm_dsim_glb) array. This patch initializes the id to -1 and checks for negative in the manager cleanup. Cc: Doug Anderson Reviewed-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm: update generated headers

2018-08-10T22:49:18Z

Resync generated headers to pull in a6xx registers. Signed-off-by: Rob Clark

drm/msm: dsi: Handle dual-channel for 6G as well

2018-07-30T12:50:12Z

This fixes up a collision between introducing dual-channel support and the dsi refactors. This patch applies the same dual-channel considerations and pclk calculations to both v2 and 6G, with a bit of abstracting for good measure. Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor

2018-07-26T14:40:15Z

Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar Cc: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm/dsi: set encoder mode for DRM bridge explicitly

2018-07-26T14:40:14Z

Currently, DRM bridge for DPU relies on the default video mode setting to set the encoder mode. Add an explicit call to set the encoder mode for bridges. Changes in v3: - None Reviewed-by: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm/dsi: initialize postdiv_lock before use for 10nm pll

2018-07-26T14:40:14Z

postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul Signed-off-by: Rob Clark