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<title>kernel.git/drivers/gpu/drm/msm/dsi, branch linux-4.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.10.y</id>
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<updated>2016-11-30T23:25:58Z</updated>
<entry>
<title>Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next</title>
<updated>2016-11-30T23:25:58Z</updated>
<author>
<name>Dave Airlie</name>
</author>
<published>2016-11-30T23:25:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f5590134365f6f23dba723f140f72effcc71773f'/>
<id>urn:sha1:f5590134365f6f23dba723f140f72effcc71773f</id>
<content type='text'>
On the userspace side, all the basics are working, and most of glmark2
is working.  I've been working through deqp, and I've got a couple more
things to fix (but we've gone from 70% to 80+% pass in last day, and
current deqp run that is going should pick up another 5-10%).  I expect
to push the mesa patches today or tomorrow.

There are a couple more a5xx related patches to take the gpu out of
secure mode (for the devices that come up in secure mode, like the hw
I have), but those depend on an scm patch that would come in through
another tree.  If that can land in the next day or two, there might
be a second late pull request for drm/msm.

In addition to the new-shiny, there have also been a lot of overlay/
plane related fixes for issues found using drm-hwc2 (in the process of
testing/debugging the atomic/kms fence patches), resulting in rework
to assign hwpipes to kms planes dynamically (as part of global atomic
state) and also handling SMP (fifo) block allocation atomically as
part of the -&gt;atomic_check() step.  All those patches should also help
out atomic weston (when those patches eventually land).

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (36 commits)
  drm/msm: gpu: Add support for the GPMU
  drm/msm: gpu: Add A5XX target support
  drm/msm: Disable interrupts during init
  drm/msm: Remove 'src_clk' from adreno configuration
  drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7
  drm/msm: Add adreno_gpu_write64()
  drm/msm: gpu Add new gpu register read/write functions
  drm/msm: gpu: Return error on hw_init failure
  drm/msm: gpu: Cut down the list of "generic" registers to the ones we use
  drm/msm: update generated headers
  drm/msm/adreno: move scratch register dumping to per-gen code
  drm/msm/rd: support for 64b iova
  drm/msm: convert iova to 64b
  drm/msm: set dma_mask properly
  drm/msm: Remove bad calls to of_node_put()
  drm/msm/mdp5: move LM bounds check into plane-&gt;atomic_check()
  drm/msm/mdp5: dump smp state on errors too
  drm/msm/mdp5: add debugfs to show smp block status
  drm/msm/mdp5: handle SMP block allocations "atomically"
  drm/msm/mdp5: dynamically assign hw pipes to planes
  ...
</content>
</entry>
<entry>
<title>drm/msm: update generated headers</title>
<updated>2016-11-28T20:14:10Z</updated>
<author>
<name>Rob Clark</name>
</author>
<published>2016-11-07T19:53:49Z</published>
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<id>urn:sha1:a26ae754b0ac086151b84a2e8db10b3e98096f2d</id>
<content type='text'>
Pull in a5xx registers.

Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: convert iova to 64b</title>
<updated>2016-11-28T20:14:08Z</updated>
<author>
<name>Rob Clark</name>
</author>
<published>2016-11-11T17:06:46Z</published>
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<id>urn:sha1:78babc1633c4b0664ea516500c2ace9bf1f17bc7</id>
<content type='text'>
For a5xx the gpu is 64b so we need to change iova to 64b everywhere.  On
the display side, iova is still 32b so it can ignore the upper bits.
(Although all the armv8 devices have an iommu that can map 64b pa to 32b
iova.)

Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks</title>
<updated>2016-11-02T14:48:09Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2016-10-27T06:27:15Z</published>
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<id>urn:sha1:73b65b197024f3f9ef16a28cc9533c011e0a3f6d</id>
<content type='text'>
The DSI/HDMI PLLs in MSM require resources like interface clocks, power
domains to be enabled before we can access their registers.

The clock framework doesn't have a mechanism at the moment where we can
tie such resources to a clock, so we make sure that the KMS driver enables
these resources whenever a PLL is expected to be in use.

One place where we can't ensure the resource dependencies are met is when
the clock framework tries to disable unused clocks. The KMS driver doesn't
know when the clock framework calls the is_enabled clk_op, and hence can't
enable interface clocks/power domains beforehand.

We set the CLK_IGNORE_UNUSED flag for PLL clocks for now. This needs to be
revisited, since bootloaders can enable display, and we would want to
disable the PLL clocks if there isn't a display driver using them.

Cc: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Queue HPD helper work in attach/detach callbacks</title>
<updated>2016-11-02T14:48:09Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2016-10-25T06:47:59Z</published>
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<id>urn:sha1:8d23ea403044efe97553dd64228b172c8ffca047</id>
<content type='text'>
The msm/dsi host drivers calls drm_helper_hpd_irq_event in the
mipi_dsi_host attach/detatch callbacks.

mipi_dsi_attach()/mipi_dsi_detach() from a panel/bridge
driver could be called from a context where the drm_device's
mode_config.mutex is already held, resulting in a deadlock.
Queue it as work instead.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Fix return value check in msm_dsi_host_set_display_mode()</title>
<updated>2016-07-16T14:29:28Z</updated>
<author>
<name>Wei Yongjun</name>
</author>
<published>2016-06-18T17:26:37Z</published>
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<id>urn:sha1:2abe1f2509bf4976dce9a220cab3f1424f0cbb0f</id>
<content type='text'>
In case of error, the function drm_mode_duplicate() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.

Signed-off-by: Wei Yongjun &lt;yongjun_wei@trendmicro.com.cn&gt;
Reviewed-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: change gem-&gt;vmap() to get/put</title>
<updated>2016-07-16T14:09:07Z</updated>
<author>
<name>Rob Clark</name>
</author>
<published>2016-05-26T20:24:35Z</published>
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<id>urn:sha1:18f23049f640e2590930c34009418c66e6ebf7b6</id>
<content type='text'>
Before we can add vmap shrinking, we really need to know which vmap'ings
are currently being used.  So switch to get/put interface.  Stubbed put
fxns for now.

Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Don't get DSI index from DT</title>
<updated>2016-07-16T14:09:02Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2016-06-23T09:56:04Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=32280d66fd44de231b1d1a015e4ef41cac2d295c'/>
<id>urn:sha1:32280d66fd44de231b1d1a015e4ef41cac2d295c</id>
<content type='text'>
The DSI host and PHY driver currently expects the DT bindings to provide
custom properties "qcom,dsi-host-index" and "qcom,dsi-phy-index" so that
the driver can identify which DSI instance it is.

The binding isn't acceptable, but the driver still needs to figure out
what its instance id. This is now done by storing the mmio starting
addresses for each DSI instance in every SoC version in the driver. The
driver then identifies the index number by trying to match the stored
address with comparing the resource start address we get from DT.

We don't have compatible strings for DSI PHY on each SoC, but only the
DSI PHY type. We only support one SoC version for each PHY type, so we
get away doing the same thing above for the PHY driver. We can revisit
this when we support two SoCs with the same DSI PHY.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Use a standard DT binding for data lanes</title>
<updated>2016-07-16T14:08:47Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2016-06-08T10:44:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=60282cea5bfa934694decfe836ee4600504bdeb1'/>
<id>urn:sha1:60282cea5bfa934694decfe836ee4600504bdeb1</id>
<content type='text'>
A more standard DT binding describing data lanes already exists here:
Documentation/devicetree/bindings/media/video-interfaces.txt

Use this binding instead of "qcom,data-lane-map". One difference
in the standard binding w.r.t to the existing binding is that it
provides a logical to physical mapping instead of the other way
round. Tweak the code to translate the data the way we want it.

The MSM DSI DT bindings aren't used anywhere at the moment, so
it's okay to update this property.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Use generic PHY bindings</title>
<updated>2016-07-16T14:08:47Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2016-04-29T12:34:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=69696ea041fa7bffb04d2141f6ec997c24cf09da'/>
<id>urn:sha1:69696ea041fa7bffb04d2141f6ec997c24cf09da</id>
<content type='text'>
The DSI host links to the DSI PHY device using a custom binding. Switch to
the generic PHY bindings. The DSI PHY driver itself doesn't use the common
PHY framework for now.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
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