<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/msm/dsi/phy, branch linux-4.19.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2022-09-15T10:17:02Z</updated>
<entry>
<title>drm/msm/dsi: fix the inconsistent indenting</title>
<updated>2022-09-15T10:17:02Z</updated>
<author>
<name>sunliming</name>
</author>
<published>2022-07-19T01:56:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=89baca94d400c5e1aed8bbb2b8d53ee97bc277a6'/>
<id>urn:sha1:89baca94d400c5e1aed8bbb2b8d53ee97bc277a6</id>
<content type='text'>
[ Upstream commit 2f25a1fb4ec516c5ad67afd754334b491b9f09a5 ]

Fix the inconsistent indenting in function msm_dsi_dphy_timing_calc_v3().

Fix the following smatch warnings:

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:350 msm_dsi_dphy_timing_calc_v3() warn: inconsistent indenting

Fixes: f1fa7ff44056 ("drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: sunliming &lt;sunliming@kylinos.cn&gt;
Reviewed-by: Abhinav Kumar &lt;quic_abhinavk@quicinc.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/494662/
Link: https://lore.kernel.org/r/20220719015622.646718-1-sunliming@kylinos.cn
Signed-off-by: Abhinav Kumar &lt;quic_abhinavk@quicinc.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: invalid parameter check in msm_dsi_phy_enable</title>
<updated>2022-02-08T17:23:09Z</updated>
<author>
<name>José Expósito</name>
</author>
<published>2022-01-16T18:18:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ca63eeb70fcb53c42e1fe54e1735a54d8e7759fd'/>
<id>urn:sha1:ca63eeb70fcb53c42e1fe54e1735a54d8e7759fd</id>
<content type='text'>
commit 5e761a2287234bc402ba7ef07129f5103bcd775c upstream.

The function performs a check on the "phy" input parameter, however, it
is used before the check.

Initialize the "dev" variable after the sanity check to avoid a possible
NULL pointer dereference.

Fixes: 5c8290284402b ("drm/msm/dsi: Split PHY drivers to separate files")
Addresses-Coverity-ID: 1493860 ("Null pointer dereference")
Signed-off-by: José Expósito &lt;jose.exposito89@gmail.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Link: https://lore.kernel.org/r/20220116181844.7400-1-jose.exposito89@gmail.com
Signed-off-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY)</title>
<updated>2021-03-04T08:39:48Z</updated>
<author>
<name>Konrad Dybcio</name>
</author>
<published>2021-01-18T16:15:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d109283a1e3700d810296c311cbd7b628e981bb4'/>
<id>urn:sha1:d109283a1e3700d810296c311cbd7b628e981bb4</id>
<content type='text'>
[ Upstream commit 33a7808ce1aea6e2edc1af25db25928137940c02 ]

The previous registers were *almost* correct, but instead of
PHYs, they were pointing at DSI PLLs, resulting in the PHY id
autodetection failing miserably.

Fixes: dcefc117cc19 ("drm/msm/dsi: Add support for msm8x94")
Signed-off-by: Konrad Dybcio &lt;konrad.dybcio@somainline.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: save pll state before dsi host is powered off</title>
<updated>2020-03-11T13:14:51Z</updated>
<author>
<name>Harigovindan P</name>
</author>
<published>2020-02-06T08:56:15Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3820cfd2559632d3213297965fbb3c7e2a5b0583'/>
<id>urn:sha1:3820cfd2559632d3213297965fbb3c7e2a5b0583</id>
<content type='text'>
[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P &lt;harigovi@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY</title>
<updated>2018-04-19T14:08:16Z</updated>
<author>
<name>Abhinav Kumar</name>
</author>
<published>2018-04-17T20:50:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f1fa7ff4405697603f5e3901623533c54091f130'/>
<id>urn:sha1:f1fa7ff4405697603f5e3901623533c54091f130</id>
<content type='text'>
Currently the DSI PHY timings are hard-coded for a specific panel
for the 10nm PHY.

Replace this with the auto PHY timing calculator which can calculate
the PHY timings for any panel.

Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- None

Reviewed-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Reviewed-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Abhinav Kumar &lt;abhinavk@codeaurora.org&gt;
Signed-off-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Populate the 10nm PHY funcs</title>
<updated>2018-02-20T15:41:21Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2018-01-17T06:05:27Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ff73ff19406098f71ec7628b951e0765f1df8128'/>
<id>urn:sha1:ff73ff19406098f71ec7628b951e0765f1df8128</id>
<content type='text'>
Populate the PHY ops with the downstream driver as reference.

There are a couple of TODOs which need to be resolved:
- The PHY timings are all hardcoded for now. This needs to be replaced
  with automatic calculations once we get/understand them.
- There are some lane configuration registers which use a new
  representation between physical and logical lane mappings. For now,
  we've hardcoced them to follow the default mapping (i.e
  logical 0 -&gt; phy 0, logical 1 -&gt; phy 1 etc).

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Add skeleton 10nm PHY/PLL code</title>
<updated>2018-02-20T15:41:20Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2018-01-17T06:05:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=973e02db35c2c4036693e32ed6f250eefd8c322c'/>
<id>urn:sha1:973e02db35c2c4036693e32ed6f250eefd8c322c</id>
<content type='text'>
Add new 10nm DSI PLL/PHY files that will be used on SDM845.

Just populate empty pll/phy funcs for now. These will be filled up
later.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: check for failure on retrieving pll in dsi manager</title>
<updated>2018-02-20T15:41:20Z</updated>
<author>
<name>Lloyd Atkinson</name>
</author>
<published>2018-01-16T21:26:01Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f0efc831d9439589efaf6406695470eca93ba08d'/>
<id>urn:sha1:f0efc831d9439589efaf6406695470eca93ba08d</id>
<content type='text'>
Make msm_dsi_pll_init consistently return an error code instead
of NULL when pll initialization fails so that later pll
retrieval can check against an error code. Add checks for these
failures after retrieval of src_pll to avoid invalid pointer
dereferences later in msm_dsi_pll_get_clk_provider.

Signed-off-by: Lloyd Atkinson &lt;latkinso@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: convert to msm_clk_get()</title>
<updated>2017-10-28T15:01:33Z</updated>
<author>
<name>Rob Clark</name>
</author>
<published>2017-10-16T17:35:57Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=db9a3750eb6fec2381b4090b4f10e56fafe512fe'/>
<id>urn:sha1:db9a3750eb6fec2381b4090b4f10e56fafe512fe</id>
<content type='text'>
We already have, as a result of upstreaming the gpu bindings,
msm_clk_get() which will try to get the clock both without and with a
"_clk" suffix.  Use this in DSI code so we can drop the "_clk" suffix
in bindings while maintaing backwards compatibility.

Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
Reviewed-by: Sean Paul &lt;seanpaul@chromium.org&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Set up runtime PM for DSI</title>
<updated>2017-08-02T11:53:46Z</updated>
<author>
<name>Archit Taneja</name>
</author>
<published>2017-07-28T10:47:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f6be1121ea8aa563f5a651cf5a96742c965a95f7'/>
<id>urn:sha1:f6be1121ea8aa563f5a651cf5a96742c965a95f7</id>
<content type='text'>
Call the pm_runtime_get/put API where we need the clocks enabled.

The main entry/exit points are 1) enabling/disabling the DSI bridge
and 2) Sending commands from the DSI host to the device.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
</feed>
