kernel.git/drivers/gpu/drm/i915/intel_step.c, branch linux-5.18.y

drm/i915/tgl: Simply subplatform detection

2022-02-23T15:41:57Z

In the past we had a need to differentiate TGL U and TGL Y, there was a different voltage swing table for each subplatform and some PCI ids of this subplatforms are shared but it turned out that it was a specification mistake and the voltage swing table was indeed the same but we went ahead with that patch because we needed to differentiate TGL U and Y from TGL H and by that time TGL H was embargoed so that was the perfect way to land it upstream. Now the embargo for TGL H is long past and now we even have INTEL_TGL_12_GT1_IDS with all TGL H ids, so we can drop this PCI root check and only rely in the PCI ids to differentiate TGL U and Y from TGL H that actually has code differences. Besides the simplification this will fix issues in virtualization environments where the PCI root is virtualized and don't have the same id as actual hardware. v2: - add and set INTEL_SUBPLATFORM_UY Cc: Fred Gao Cc: Tvrtko Ursulin Signed-off-by: José Roberto de Souza Reviewed-by: Tvrtko Ursulin Tested-by: Yu He Link: https://patchwork.freedesktop.org/patch/msgid/20220222141424.35165-1-jose.souza@intel.com

drm/i915: Introduce G12 subplatform of DG2

2022-02-01T21:07:45Z

Another fork of the DG2 design has appeared, known as "DG2-G12;" let's add it as a new subplatform. As with G11, the GT stepping resets back to A0 (so a DG2-G12 A0 is similar, but not identical, to a DG2-G10 C0) but the display steppings continue to use the same numbering scheme as G10 and G11. Some existing DG2 workarounds are starting to be extended to the DG2-G12 subplatform. So far only workarounds that were "permanent" for both DG2-G10 and DG2-G11 have been tagged for DG2-G12, but more stepping-specific workarounds are likely to show up in the future. Bspec: 44477 Signed-off-by: Matt Roper Reviewed-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20220120235016.1209326-1-matthew.d.roper@intel.com

drm/i915/rpl-s: Add stepping info

2022-01-26T19:23:58Z

Add stepping-substepping info in accordance to BSpec changes. Though it looks weird, the revision ID for the newer stepping is indeed backwards and is in accordance to the spec. v2: Rearrange the platforms in logical order (Matt) Bspec: 53655 Cc: Matt Roper Signed-off-by: Anusha Srivatsa Reviewed-by: Matt Roper Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20220125223625.4139326-1-anusha.srivatsa@intel.com

drm/i915: Rename GT_STEP to GRAPHICS_STEP

2021-11-02T20:05:40Z

As now graphics and media can have different steppings this patch is renaming all _GT_STEP macros to _GRAPHICS_STEP. Future platforms will properly choose between _MEDIA_STEP and _GRAPHICS_STEP for each new workaround. Cc: Matt Atwood Cc: Radhakrishna Sripada Signed-off-by: José Roberto de Souza Reviewed-by: Caz Yokoyama Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20211020002353.193893-3-jose.souza@intel.com

drm/i915: Track media IP stepping separated from GT

2021-11-02T20:05:37Z

Graphics and media IPs can have different stepping so a new field is needed in intel_step_info. The next patch will take care of rename gt_step to graphics_step. Cc: Radhakrishna Sripada Cc: Matt Atwood Signed-off-by: José Roberto de Souza Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20211020002353.193893-2-jose.souza@intel.com

drm/i915/dg2: Add support for new DG2-G11 revid 0x5

2021-08-06T16:03:10Z

The bspec has been updated with a new revision 0x5 that translates to B1 GT stepping and C0 display stepping. Bspec: 44477 Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-2-matthew.d.roper@intel.com

drm/i915/step: Add macro magic for handling steps

2021-07-22T17:18:06Z

With the addition of stepping info for all platforms, lets use macros for handling them and autogenerating code for all steps at a time. Suggested-by: Matt Roper Cc: Lucas De Marchi Signed-off-by: Anusha Srivatsa Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20210721215238.24980-1-anusha.srivatsa@intel.com

drm/i915/dg2: add DG2 platform info

2021-07-22T16:20:41Z

DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics. There are two variants (treated as subplatforms in the code): DG2-G10 and DG2-G11 that require independent programming in some areas (e.g., workarounds). Bspec: 44472, 44474, 46197, 48028, 48077 Cc: Anusha Srivatsa Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-4-matthew.d.roper@intel.com

drm/i915/xehpsdv: add initial XeHP SDV definitions

2021-07-22T16:19:13Z

XeHP SDV is a Intel® dGPU without display. This is just the definition of some basic platform macros, by large a copy of current state of Tigerlake which does not reflect the end state of this platform. v2: - Switch to intel_step infrastructure for stepping matches. (Jani) v3: - Bring earlier in patch series and leave addition of new media engines to the engine mask for a later patch. Bspec: 44467, 48077 Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: José Roberto de Souza Signed-off-by: Stuart Summers Signed-off-by: Tomas Winkler Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-3-matthew.d.roper@intel.com

drm/i915/dg1: Use revid->stepping tables

2021-07-15T00:47:11Z

Switch DG1 to use a revid->stepping table as we're trying to do on all platforms going forward. This removes the last use of IS_REVID() and REVID_FOREVER, so remove those now-unused macros as well to prevent their accidental use on future platforms. v2: - Use COMMON_STEP() macro in table. (Anusha) Bspec: 44463 Cc: Anusha Srivatsa Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20210713193635.3390052-11-matthew.d.roper@intel.com