kernel.git/drivers/gpu/drm/i915/intel_runtime_pm.c, branch linux-5.0.y

drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI

2018-11-29T20:23:54Z

On Icelake, a separate power well PG2 is created for VDSC engine used for eDP/MIPI DSI. This patch adds a new display power domain for Power well 2. v3: * Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville) * Move it around TRANSCODER power domain defs (Ville) v2: * Fix the power well mismatch CI error (Ville) * Rename as VDSC_PIPE_A (Imre) * Fix a whitespace (Anusha) * Fix Comments (Imre) Cc: Ville Syrjala Cc: Rodrigo Vivi Cc: Imre Deak Signed-off-by: Manasi Navare Reviewed-by: Ville Syrjala Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-7-manasi.d.navare@intel.com

drm/i195: spell out reverse on for_each macros

2018-11-16T00:36:58Z

Do like it's done for list.h macros, and use "reverse" suffix rather than "rev". Signed-off-by: Lucas De Marchi Reviewed-by: Jani Nikula Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20181114011509.3667-3-lucas.demarchi@intel.com

drm/i915: Remove special case for power well 1/MISC_IO state verification

2018-11-14T11:45:36Z

Even though PW#1 and the MISC_IO power wells are managed by the DMC firmware (toggled dynamically if conditions allow it) from the driver's POV they are always on if the display core is initialized (always restored by DMC to the enabled state after exiting from DC5/6 for instance b/c of MMIO access). Accordingly we can just mark them as always-on and remove the special casing for them during state verification (thus enabling verification for these power wells too). Cc: Ramalingam C Cc: Daniel Vetter Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20181109145822.15446-3-imre.deak@intel.com

drm/i915: Use proper bool bitfield initializer in power well descs

2018-11-14T11:45:31Z

We can just use a proper true/false initializer even for bitfields, which is more descriptive. Cc: Ramalingam C Cc: Daniel Vetter Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20181109145822.15446-2-imre.deak@intel.com

drm/i915/gen9_bc: Work around DMC bug zeroing power well requests

2018-11-14T11:45:15Z

A DMC bug on GEN9 big core machines fails to restore the driver's request bits for the PW1 and MISC_IO power wells after a DC5/6 entry->exit sequence. As a consequence the driver's subsequent check for the enabled status of these power wells will fail, as the check considers the power wells being enabled only if both the status and request bits are set. To work around this borrow the request bits from BIOS's own request register in which DMC forces on the request bits when exiting from DC5/6. This fixes a problem reported by Ramalingam, where HDCP init failed, since PW1 reported itself as being disabled, while in reality it was enabled. Reported-by: Ramalingam C Cc: Ramalingam C Cc: Daniel Vetter Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20181109145822.15446-1-imre.deak@intel.com

drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update

2018-11-14T09:36:58Z

Register DBUF_CTL_S2 is read and it's value is not used. As there is no explanation why we should prime the hardware with read, remove it as spurious. Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed") Cc: Mahesh Kumar Cc: Rodrigo Vivi Signed-off-by: Mika Kuoppala Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20181109140924.2663-1-mika.kuoppala@linux.intel.com

drm/i915/icl: Fix port B combo PHY context loss after DC transitions

2018-11-08T17:27:29Z

On ICL DMC/PCODE retains the HW context only for port A across DC transitions, for the other port B combo PHY, it doesn't. So we need to do this manually after exiting from DC6. Do the reinit even after exiting from DC5, it won't hurt since we only reinit the PHY in case it's needed (in case it was disabled to begin with). As can be guessed from the bugzilla report leaving the PHY uninited will lead to a later timeout during the port B specific AUX and DDI_IO power well enabling. v2: - Apply the fix on all GEN>=11 platforms. (Rodrigo) Bspec: 21257 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108070 Cc: Paulo Zanoni Cc: Ville Syrjälä Cc: José Roberto de Souza Cc: Rodrigo Vivi Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20181106160621.23057-6-imre.deak@intel.com

drm/i915/cnl+: Move the combo PHY init/uninit code to a new file

2018-11-08T17:27:00Z

Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code in a separate file. No functional change. v2: - Use SPDX license tag instead of boilerplate. (Rodrigo) v3: - Use MIT instead of GPL-2.0 license. (Ville) Suggested-by: Ville Syrjälä Cc: Paulo Zanoni Cc: Ville Syrjälä Cc: José Roberto de Souza Cc: Rodrigo Vivi Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20181106160621.23057-3-imre.deak@intel.com

drm/i915/icl: Fix combo PHY uninit

2018-11-08T17:23:57Z

BSpec says to clear the comp init HW flag too during combo PHY uninit, so do that. The lack of this could badly interact with the PHY reinit after a DC6/9 transition at least, where (after a follow-up patch fixing the init code) we'd skip the initialization incorrectly due to this flag being set. BSpec: 21257 Cc: Paulo Zanoni Cc: Ville Syrjälä Cc: José Roberto de Souza Cc: Rodrigo Vivi Signed-off-by: Imre Deak Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20181106160621.23057-2-imre.deak@intel.com

drm/i915/icl: Fix power well 2 wrt. DC-off toggling order

2018-11-07T20:19:24Z

To enable DC5/6 power well 2 has to be disabled as for previous platforms, so fix things up. Bspec: 4234 Fixes: 67ca07e7ac10 ("drm/i915/icl: Add power well support") Cc: Animesh Manna Cc: Paulo Zanoni Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20181102182200.17219-1-imre.deak@intel.com