kernel.git/drivers/gpu/drm/i915/i915_cmd_parser.c, branch linux-4.7.y

drm/i915: Bump command parser version for new whitelisted registers

2016-03-21T09:03:26Z

Signed-off-by: Jordan Justen Reviewed-by: Francisco Jerez Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-6-git-send-email-jordan.l.justen@intel.com

drm/i915: Add Haswell CS GPR registers to whitelist

2016-03-21T09:03:17Z

This is needed for the Mesa Vulkan driver on Haswell. Signed-off-by: Jordan Justen Reviewed-by: Francisco Jerez Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-5-git-send-email-jordan.l.justen@intel.com

drm/i915: Move Haswell registers to separate whitelist table

2016-03-21T09:02:46Z

Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1 and HSW_ROW_CHICKEN3 into a separate Haswell only table. Signed-off-by: Jordan Justen Cc: Francisco Jerez Reviewed-by: Francisco Jerez Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-4-git-send-email-jordan.l.justen@intel.com

drm/i915: Use an array of register tables in command parser

2016-03-21T09:02:01Z

For Haswell, we will want another table of registers while retaining the large common table of whitelisted registers shared by all gen7 devices. Signed-off-by: Jordan Justen Reviewed-by: Francisco Jerez [danvet: Pipe patch through sed -e 's/\/engine/g' to make it apply.] Signed-off-by: Daniel Vetter

drm/i915: Add TIMESTAMP to register whitelist

2016-03-21T08:56:42Z

This is needed for the Mesa Vulkan driver on Haswell. Signed-off-by: Jordan Justen Cc: Kristian Høgsberg Cc: Kenneth Graunke Reviewed-by: Francisco Jerez Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-2-git-send-email-jordan.l.justen@intel.com

drm/i915: Rename intel_engine_cs function parameters

2016-03-16T15:33:10Z

@@ identifier func; @@ func(..., struct intel_engine_cs * - ring + engine , ...) { <... - ring + engine ...> } @@ identifier func; type T; @@ T func(..., struct intel_engine_cs * - ring + engine , ...); Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson

drm/i915: Type safe register read/write

2015-11-18T13:39:11Z

Make I915_READ and I915_WRITE more type safe by wrapping the register offset in a struct. This should eliminate most of the fumbles we've had with misplaced parens. This only takes care of normal mmio registers. We could extend the idea to other register types and define each with its own struct. That way you wouldn't be able to accidentally pass the wrong thing to a specific register access function. The gpio_reg setup is probably the ugliest thing left. But I figure I'd just leave it for now, and wait for some divine inspiration to strike before making it nice. As for the generated code, it's actually a bit better sometimes. Eg. looking at i915_irq_handler(), we can see the following change: lea 0x70024(%rdx,%rax,1),%r9d mov $0x1,%edx - movslq %r9d,%r9 - mov %r9,%rsi - mov %r9,-0x58(%rbp) - callq *0xd8(%rbx) + mov %r9d,%esi + mov %r9d,-0x48(%rbp) callq *0xd8(%rbx) So previously gcc thought the register offset might be signed and decided to sign extend it, just in case. The rest appears to be mostly just minor shuffling of instructions. v2: i915_mmio_reg_{offset,equal,valid}() helpers added s/_REG/_MMIO/ in the register defines mo more switch statements left to worry about ring_emit stuff got sorted in a prep patch cmd parser, lrc context and w/a batch buildup also in prep patch vgpu stuff cleaned up and moved to a prep patch all other unrelated changes split out v3: Rebased due to BXT DSI/BLC, MOCS, etc. v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/ Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com

drm/i915: Make the cmd parser 64bit regs explicit

2015-11-18T12:35:20Z

Add defines for the upper halves of the registers used by the cmd parser. Getting rid of the arithmetic with the register offset will help in making registers type safe. v2: s/_HI/_UDW/ (Chris) Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson Link: http://patchwork.freedesktop.org/patch/msgid/1446839080-18732-1-git-send-email-ville.syrjala@linux.intel.com

drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelist

2015-10-06T08:40:22Z

This is required to support glDispatchComputeIndirect for gen7. Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsberg Signed-off-by: Daniel Vetter

drm/i915: Fix cmdparser STORE/LOAD command descriptors

2015-09-04T08:43:09Z

Fixes regression from commit f1afe24f0e736b9d7f2275e2b1504af3fe612f2a Author: Arun Siluvery Date: Tue Aug 4 16:22:20 2015 +0100 drm/i915: Change SRM, LRM instructions to use correct length which forgot to account for the length bias when declaring the fixed length. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91844 Reported-by: Andreas Reis Signed-off-by: Chris Wilson Cc: Dave Gordon Cc: Arun Siluvery Cc: Mika Kuoppala Cc: Daniel Vetter Reviewed-by: Arun Siluvery Signed-off-by: Daniel Vetter