kernel.git/drivers/gpu/drm/amd/include/asic_reg, branch linux-6.14.yHosts the 0x221E linux distro kernel.
https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y2025-05-29T09:13:25Zdrm/amdgpu: Set snoop bit for SDMA for MI series2025-05-29T09:13:25ZHarish Kasiviswanathan2025-02-04T22:57:47Zurn:sha1:b99de2f1be2adcac73ca0ec2b75561baa3a54510
[ Upstream commit 3394b1f76d3f8adf695ceed350a5dae49003eb37 ]
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.
v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
Modified function names based on review comments.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu: rename register headers to dcn_2_0_12024-12-10T15:37:34ZLeo Li2024-12-05T20:43:42Zurn:sha1:ecc5278ce05d18fb0a2e167ead91394356cb4c79
They were named with the incorrect dcn version.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Sun peng Li <sunpeng.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add umc v8_14_0 ip headers2024-12-10T15:28:31ZCandice Li2024-07-11T08:45:10Zurn:sha1:334a81583e6cb722a99b6897cae6e63ea4fb16f5
Add umc v8_14_0 ip headers.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add some missing straps from NBIO 7.11.02024-11-20T15:02:53ZMario Limonciello2024-11-18T17:46:10Zurn:sha1:902fbbf429b8213232b18de0ddfd5c0f3851cb8f
Earlier ASICs have strap information exported, and this is missing
for NBIO 7.11.0.
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers")
Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add a missing DCN401 reg definition2024-11-04T16:40:21ZAurabindo Pillai2024-11-01T16:16:18Zurn:sha1:c7b4ecc1fa29235e5a14ad178ab96ef15a0d16f6
Add a mising reg field to the autogenerated header for future use
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: init saw registers for mmhub v1.02024-10-22T21:49:38ZZhu Lingshan2024-09-25T03:09:51Zurn:sha1:9ee8ab245c4f4d6a38598b4f14d33c6581c4cce6
This commits init registers in the Stand Along Walker
for mmhub v1.0, to support ISP use cases.
Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
Reported-and-tested-by: Du Bin <bin.du@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/uvd4: fix mask and shift definitions2024-08-13T14:26:48ZRemington Brasga2024-07-31T05:54:51Zurn:sha1:3834ce360067b4ee98fdef14571923500a0499a4
A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.
Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix atomics on GFX122024-07-23T21:33:17ZDavid Belanger2024-06-10T20:38:55Zurn:sha1:666f14cab21b17ccc1bdfe1e82458aa429b3b7e0
If PCIe supports atomics, configure register to prevent DF from
breaking atomics in separate load/store operations.
Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add some missing register definitions2024-06-27T21:32:17ZAurabindo Pillai2024-06-25T18:17:46Zurn:sha1:ad89e904e3aaa93628785546034ec77f3100cf79
Add some register offsets that are required for Display DCC on DCN401
Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add reg definitions for DCN401 DCC2024-06-27T21:10:38ZAurabindo Pillai2024-06-14T19:42:55Zurn:sha1:2d072b445622b90f8a961c0376887120da75221f
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>