<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/include/asic_reg/oss, branch linux-6.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2024-04-19T03:46:31Z</updated>
<entry>
<title>drm/amdgpu: add IH_RING1_CFG headers for IH v6.0</title>
<updated>2024-04-19T03:46:31Z</updated>
<author>
<name>Sunil Khatri</name>
</author>
<published>2024-04-12T09:17:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cba9b630f087005a2c9c201e16b5dbf91d51d3c0'/>
<id>urn:sha1:cba9b630f087005a2c9c201e16b5dbf91d51d3c0</id>
<content type='text'>
Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri &lt;sunil.khatri@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add osssys v7_0_0 ip headers (v4)</title>
<updated>2024-02-12T21:09:06Z</updated>
<author>
<name>Hawking Zhang</name>
</author>
<published>2023-12-19T11:10:26Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=33c0c80ae5e9c2800794aa208902c144b9a21f7b'/>
<id>urn:sha1:33c0c80ae5e9c2800794aa208902c144b9a21f7b</id>
<content type='text'>
v1: Add osssys v7_0_0 register offset and shift masks
    header files. (Hawking)
v2: Update osssys v7_0_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update osssys v7_0_0 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Clean up osssys v7_0_0 ip headers (Alex)

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add ih 6.1 registers</title>
<updated>2023-08-07T20:35:31Z</updated>
<author>
<name>Ben Li</name>
</author>
<published>2023-07-14T19:41:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=85c391abd2c64d59e34065c7a9e1c192a8309ec5'/>
<id>urn:sha1:85c391abd2c64d59e34065c7a9e1c192a8309ec5</id>
<content type='text'>
Add new registers.

v2: updates (Alex)

Signed-off-by: Ben Li &lt;ben.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable IH retry CAM on GFX9</title>
<updated>2023-04-13T04:14:08Z</updated>
<author>
<name>Mukul Joshi</name>
</author>
<published>2023-04-11T20:32:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=318e431b306e966d2ee99e900a11bdc9a701ee83'/>
<id>urn:sha1:318e431b306e966d2ee99e900a11bdc9a701ee83</id>
<content type='text'>
This patch enables the IH retry CAM on GFX9 series cards. This
retry filter is used to prevent sending lots of retry interrupts
in a short span of time and overflowing the IH ring buffer. This
will also help reduce CPU interrupt workload.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add osssys v4_4_2 ip headers</title>
<updated>2023-03-31T15:18:43Z</updated>
<author>
<name>Hawking Zhang</name>
</author>
<published>2022-04-24T06:40:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=40a9634b4f09a63f69a373af5d4ca7e69e6a78ad'/>
<id>urn:sha1:40a9634b4f09a63f69a373af5d4ca7e69e6a78ad</id>
<content type='text'>
Add osssys v4_4_2 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Le Ma &lt;Le.Ma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add osssys v6_0_0 ip headers v4</title>
<updated>2022-05-04T13:52:56Z</updated>
<author>
<name>Hawking Zhang</name>
</author>
<published>2021-12-30T11:21:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d71093aa15f018ec005a31a131068f46653900ac'/>
<id>urn:sha1:d71093aa15f018ec005a31a131068f46653900ac</id>
<content type='text'>
Add osssys v6_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add osssys v4_2 ip headers (v2)</title>
<updated>2020-12-23T20:05:20Z</updated>
<author>
<name>Hawking Zhang</name>
</author>
<published>2020-12-08T09:22:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=502173ac2386c9e417ccf75e5e84241d52f41702'/>
<id>urn:sha1:502173ac2386c9e417ccf75e5e84241d52f41702</id>
<content type='text'>
v1: add osssys v4_2 register offset and shift masks
header files. vega20 and arcturus will refer to
these ip headers. (Hawking)
v2: clean up osssys v4_2 registers (Alex)

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Dennis Li &lt;Dennis.Li@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: add IH cg support on soc15 project</title>
<updated>2019-10-03T14:11:04Z</updated>
<author>
<name>Kenneth Feng</name>
</author>
<published>2019-09-25T05:41:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=227f7d58d707fa6d931a1e16d29eb3e1c41ad67d'/>
<id>urn:sha1:227f7d58d707fa6d931a1e16d29eb3e1c41ad67d</id>
<content type='text'>
enable/disable IH clock gating on soc15 projects.

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header for VG/RV series</title>
<updated>2019-08-30T20:37:17Z</updated>
<author>
<name>Aaron Liu</name>
</author>
<published>2018-12-14T03:16:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=75966255881127f4a2c0ab7e18d9224672bdeddb'/>
<id>urn:sha1:75966255881127f4a2c0ab7e18d9224672bdeddb</id>
<content type='text'>
In Renoir's emulator, those chicken bits need to be programmed.

Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add OSS 5.0 register headers</title>
<updated>2019-06-20T20:54:42Z</updated>
<author>
<name>Hawking Zhang</name>
</author>
<published>2019-03-03T03:30:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3d220cc3bde54df9fdfbe40458e580971723b767'/>
<id>urn:sha1:3d220cc3bde54df9fdfbe40458e580971723b767</id>
<content type='text'>
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
