kernel.git/drivers/gpu/drm/amd/display/dmub, branch linux-6.14.y

drm/amd/display: Support multiple options during psr entry.

2025-05-29T09:13:26Z

[ Upstream commit 3a5fa55455db6a11248a25f24570c365f9246144 ] [WHY] Some panels may not handle idle pattern properly during PSR entry. [HOW] Add a condition to allow multiple options on power down sequence during PSR1 entry. Reviewed-by: Anthony Koo Signed-off-by: Martin Tsai Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix DMUB reset sequence for DCN401

2025-05-29T09:12:57Z

[ Upstream commit 0dfcc2bf269010a6e093793034c048049a40ee93 ] [WHY] It should no longer use DMCUB_SOFT_RESET as it can result in the memory request path becoming desynchronized. [HOW] To ensure robustness in the reset sequence: 1) Extend timeout on the "halt" command sent via gpint, and check for controller to enter "wait" as a stronger guarantee that there are no requests to memory still in flight. 2) Remove usage of DMCUB_SOFT_RESET 3) Rely on PSP to reset the controller safely Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Ensure DMCUB idle before reset on DCN31/DCN35

2025-05-29T09:12:56Z

[ Upstream commit c707ea82c79dbd1d295ec94cc6529a5248c77757 ] [Why] If we soft reset before halt finishes and there are outstanding memory transactions then the memory interface may produce unexpected results, such as out of order transactions when the firmware next runs. These can manifest as random or unexpected load/store violations. [How] Increase the timeout before soft reset to ensure the DMCUB has quiesced. This is effectively 1s maximum based on experimentation. Use the enable bit check on DCN31 like we're doing on DCN35 and reorder the reset writes to follow the HW programming guide. Ensure we're reading SCRATCH7 instead of SCRATCH8 for the HALT code. No current versions of DMCUB firmware use the SCRATCH8 boot bit to dynamically switch where the HALT code goes to maintain backwards compatibility with PSP. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix incorrect fw_state address in dmub_srv

2025-03-18T20:33:38Z

[WHY] The fw_state in dmub_srv was assigned with wrong address. The address was pointed to the firmware region. [HOW] Fix the firmware state by using DMUB_DEBUG_FW_STATE_OFFSET in dmub_cmd.h. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Lo-an Chen Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher (cherry picked from commit f57b38ac85a01bf03020cc0a9761d63e5c0ce197)

drm/amd/display: [FW Promotion] Release 0.0.248.0

2025-01-10T17:00:01Z

Refactoring some flags for replay Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Implement Replay Low Hz Visual Confirm

2025-01-06T19:44:27Z

[why] Add new Visual confirm color for Replay Low Hz. Reviewed-by: Robin Chen Signed-off-by: Dennis.Chan Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: [FW Promotion] Release 0.0.246.0

2024-12-10T15:37:21Z

Reviewed-by: Leo Li Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Make DMCUB tracebuffer debugfs chronological

2024-12-10T15:32:03Z

[Why] Previously, the debugfs did a simple dump of the tracebuffer region. Because the tracebuffer is a ring, it meant that the entries printed may not be in chronological order if the ring rolled over. This makes parsing the tracelog cumbersome. [How] Since dmcub provides the current entry count, use that to determine the latest tracelog entry and output the log chronologically. Also, the fb region size is not accurate of the actual tracebuffer size; it has been padded to alignment requirements. Use the tracebuffer size reported by the fw meta_info, if available. If not, a fallback to the hardcoded default is needed. To make this value available to other .c files, its define was moved to dmub_srv.h. Also, print a indicator at the start of the log if rollover occurred. Reviewed-by: Harry Wentland Signed-off-by: Leo Li Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: 3.2.309

2024-11-11T16:54:53Z

This version brings along the following: - DML2 fixes - DP fixes - DPMS fix - HPD fixes - Misc cleanup - ODM fix - Replay fix - SPL fix Reviewed-by: Leo Li Signed-off-by: Aric Cyr Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Use region6 size in fw_meta_info

2024-11-08T16:45:30Z

[Why] If driver allocated region6 size is not same as the size in firmware, dmcub won't enable region6. [How] Use region6 size in dmcub_fw_meta instead of a constant value. Reviewed-by: Nicholas Kazlauskas Signed-off-by: JinZe Xu Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher