kernel.git/drivers/gpu/drm/amd/display/dmub/src, branch linux-5.17.y

drm/amd/display: Fix check for null function ptr

2021-12-30T13:54:44Z

[Why] Bug fix for null function ptr (should check for NULL instead of not NULL) [How] Fix if condition Tested-by: Daniel Wheeler Reviewed-by: Samson Tam Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: Clean up some inconsistent indenting

2021-11-22T19:45:02Z

Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:622 dmub_srv_cmd_execute() warn: inconsistent indenting. Reported-by: Abaci Robot Reviewed-by: Christian König Signed-off-by: Jiapeng Chong Signed-off-by: Alex Deucher

drm/amd/display: Only flush delta from last command execution

2021-11-22T19:45:01Z

[Why] We're currently flushing commands that had been previously been flushed or are currently being processed by the DMCUB when we don't immediately wait for idle after command execution. [How] Avoiding reflushing the data by keeping track of the last wptr. We'll treat this as the actual rptr by creating a copy of the inbox and modifying the copy's rptr. Reviewed-by: Eric Yang Acked-by: Wayne Lin Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Wait for ACK for INBOX0 HW Lock

2021-11-17T21:58:11Z

[Why] In DC we want to wait for the INBOX0 HW Lock command to ACK before continuing. This is to ensure that the lock has been successfully acquired before programming HW in DC. [How] Add interfaces to send messages on INBOX0, poll for their completation and clear the ack. Reviewed-by: Nicholas Kazlauskas Acked-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: Fix detection of aligned DMUB firmware meta info

2021-11-17T21:58:06Z

[Why] A built firmware binary may be aligned to 16-bytes with padding at the end as necessary. In the case that padding was applied the meta info will not be detected correctly and we won't be able to allocate the appropriate firmware and tracebuffer sizes. [How] To maintain compatibility with already released firmware where this occurs we need to try every meta offset from 0..15 inclusive. Extract out the meta info checker into a helper function that's called for each of these offsets and exit early when we've found it. Reviewed-by: Eric Yang Acked-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/display: Added new DMUB boot option for power optimization

2021-11-03T16:32:34Z

[Why] During Z10, root clock gating and memory low power registers needs to to be restored if optimization is enabled in driver. [How] Added new DMUB boot option for root clock gating and memory low power. Acked-by: Aurabindo Pillai Signed-off-by: Jake Wang Reviewed-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Enable dpia in dmub only for DCN31 B0

2021-10-28T18:26:59Z

[Why] DMUB binary is common for both A0 and B0. Hence, driver should notify FW about the support for DPIA in B0. [How] Added dpia_supported bit in dmub_fw_boot_options and will be set only for B0. Assign dpia_supported to true before dm_dmub_hw_init in B0 case. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Signed-off-by: Jude Shih Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/display: Set phy_mux_sel bit in dmub scratch register

2021-10-28T18:26:16Z

[Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin Cc: Nicholas Kazlauskas Reviewed-by: Charlene Liu Acked-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Hansen Signed-off-by: Alex Deucher

drm/amd/display: Add dpia debug options

2021-10-06T19:52:24Z

[Why & How] To add support for dpia debug options. Reviewed-by: Jimmy Kizito Acked-by: Wayne Lin Acked-by: Nicholas Kazlauskas Acked-by: Harry Wentland Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Alex Deucher

drm/amd/display: Support for SET_CONFIG processing with DMUB

2021-10-06T19:52:11Z

[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async(). DMUB processes the command with DPIA sends reply back immediately or in an outbox1 message triggering an outbox1 interrupt to driver. 2) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 3) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by: Jun Lei Acked-by: Wayne Lin Acked-by: Nicholas Kazlauskas Acked-by: Harry Wentland Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Alex Deucher