kernel.git/drivers/gpu/drm/amd/display/dc/resource, branch linux-6.16.y

drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming.

2025-08-28T14:34:31Z

commit 1c8dc3e088e09531bcdfc9fe348204abc3decb6c upstream. Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only be used for DP. Make sure to initialize the correct amount of PLLs in DC for these DCE versions and use PLL0 only for DP. Also, on DCE 6.0 and 6.4, the PLL0 needs to be powered on at initialization as opposed to DCE 6.1 and 7.x which use a different clock source for DFS. The following functions were used as reference from the old radeon driver implementation of DCE 6.x: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher (cherry picked from commit 35222b5934ec8d762473592ece98659baf6bc48e) Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Disable dsc_power_gate for dcn314 by default

2025-08-20T16:41:21Z

[ Upstream commit 02f3ec53177243d32ee8b6f8ba99136d7887ee3a ] [Why] "REG_WAIT timeout 1us * 1000 tries - dcn314_dsc_pg_control line" warnings seen after resuming from s2idle. DCN314 has issues with DSC power gating that cause REG_WAIT timeouts when attempting to power down DSC blocks. [How] Disable dsc_power_gate for dcn314 by default. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Roman Li Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Add dc cap for dp tunneling

2025-06-18T16:59:45Z

[WHAT] 1. add dc cap for dp tunneling 2. add function to get index of host router Cc: Mario Limonciello Cc: Alex Deucher Reviewed-by: Cruise Hung Signed-off-by: Peichen Huang Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher (cherry picked from commit 29e178d13979cf6fdb42c5fe2dfec2da2306c4ad) Cc: stable@vger.kernel.org

drm/amd/display: no 3D and blnd LUT as DPP color caps for DCN401

2025-05-22T16:02:33Z

Match what is declared as DPP color caps with hw caps. DCN401 has MPC shaper + 3D LUTs that are movable before and after blending (get from plane or stream), but no DPP blend LUTs. Signed-off-by: Melissa Wen Reviewed-by: Alex Hung Signed-off-by: Alex Deucher

drm/amd/display: Assign preferred stream encoder instance to dpia

2025-05-05T17:28:47Z

[Why] For dpia, preferred engine instance availability is not checked when assigning stream encoder instance. [How] Check for dpia preferred engine id and assign the same stream encoder instance for the stream if available. Reviewed-by: PeiChen Huang Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Refactor SubVP cursor limiting logic

2025-05-05T16:58:49Z

[WHY] There are several gaps that can result in SubVP being enabled with incompatible HW cursor sizes, and unjust restrictions to cursor size due to wrong predictions on future usage of SubVP. [HOW] - remove "prediction" logic in favor of tagging based on previous SubVP usage - block SubVP if current HW cursor settings are incompatible - provide interface for DM to determine if HW cursor should be disabled due to an attempt to enable SubVP Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END

2025-05-05T16:58:30Z

[WHY & HOW] Remove the unnecessary DC_FP_START/DC_FP_END pair to reduce time in preempt_disable. It also fixes "BUG: sleeping function called from invalid context" error messages because of calling kzalloc with GFP_KERNEL which can sleep. Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Hung Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

Revert "drm/amd/display: Refactor SubVP cursor limiting logic"

2025-05-05T16:55:35Z

This reverts commit 19e743f0fb73 ("drm/amd/display: Refactor SubVP cursor limiting logic") Reason for revert: Corruption Reviewed-by: Alvin Lee Signed-off-by: Ryan Seto Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Update IPS sequential_ono requirement checks

2025-05-05T16:54:12Z

[why & how] ASICs that require special RCG/PG programming are determined based on hw_internal_rev. Update these checks to properly include all such ASICs. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Refactor SubVP cursor limiting logic

2025-04-22T12:51:45Z

[WHY] There are several gaps that can result in SubVP being enabled with incompatible HW cursor sizes, and unjust restrictions to cursor size due to wrong predictions on future usage of SubVP [HOW] - remove "prediction" logic in favor of tagging based on previous SubVP usage - block SubVP if current HW cursor settings are incompatible - provide interface for DM to determine if HW cursor should be disabled due to an attempt to enable SubVP Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Zaeem Mohamed Tested-by: Mark Broadworth Signed-off-by: Alex Deucher