kernel.git/drivers/gpu/drm/amd/display/dc/link/protocols, branch linux-6.5.y

drm/amd/display: Work around bad DPCD state on link loss

2023-06-30T17:11:35Z

[Why] This display doesn't properly indicate link loss through DPCD bits such as CR_DONE / CHANNEL_EQ_DONE / SYMBOL_LOCKED / INTERLANE_ALIGN_DONE, which all remain set. In addition, DPCD200Eh doesn't match the value of DPCD204h in all cases. For these reasons, we can miss re-training the link, since we don't properly detect link loss with this display. [Why] Add display-specific workaround to read DPCD204h, so that we can detect link loss based on 128b132b-specific status bits in this register. Tested-by: Daniel Wheeler Reviewed-by: Wenjing Liu Acked-by: Rodrigo Siqueira Signed-off-by: Ilya Bakoulin Signed-off-by: Alex Deucher

drm/amd/display: Fix 128b132b link loss handling

2023-06-23T19:45:48Z

[Why] We don't check 128b132b-specific bits in LANE_ALIGN_STATUS_UPDATED DPCD registers when parsing link loss status, which can cause us to miss a link loss notification from some sinks. [How] Add a 128b132b-specific status bit check. Cc: stable@vger.kernel.org # 6.3+ Reviewed-by: Wenjing Liu Acked-by: Hamza Mahfooz Signed-off-by: Ilya Bakoulin Signed-off-by: Alex Deucher

drm/amd/display: Clean FPGA code in dc

2023-06-09T14:44:11Z

[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by: Ariel Bernstein Acked-by: Tom Chung Signed-off-by: Qingqing Zhuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: lower dp link training message level

2023-06-09T14:42:39Z

[Why] some test apps report dp link training waring even dp training pass. there are 4 tries of lt within perform_link_training_with_retries. if lt pass within 4 tries, it will NOT be reated as lt failure. for each try of lt, if lt fails, current driver implementation prints message at warning level. this let people think dp lt does not work properly. [How] for 1st, 2nd and 3rd try of lt, print message at debug level. for the 4th try of lt, print message at warning level. Reviewed-by: Jerry Zuo Acked-by: Tom Chung Signed-off-by: Hersen Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add logging when DP link training Channel EQ is Successful

2023-06-09T13:27:14Z

Log when Channel Equalization is successful. Cc: Aurabindo Pillai Cc: Fangzhi Zuo Reviewed-by: Rodrigo Siqueira Signed-off-by: Srinivasan Shanmugam Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Add logging for eDP v1.4 supported sink rates

2023-06-09T13:26:39Z

Include eDP v1.4 panels supported sink rates in debug output, useful info for knowing optimized link rates Cc: Aurabindo Pillai Cc: Jerry Zuo Reviewed-by: Rodrigo Siqueira Signed-off-by: Srinivasan Shanmugam Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: DSC passthrough is for DP-HDMI pcon (SST pcon)

2023-06-09T13:21:49Z

if check over DSC passthrough is removed, as this is not for MST use case. It is for DP-HDMI pcon use case. sst pcon is detected as sst not mst. In sst pcon dsc passthrough message will not get below log printed Fixes: 9b035d089086 ("drm/amd/display: Check & log if receiver supports MST, DSC & FEC.") Suggested-by: Fangzhi Zuo Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Fangzhi Zuo Signed-off-by: Alex Deucher

drm/amd/display: Keep disable aux-i delay as 0

2023-04-24T22:36:46Z

[WHY] Current Aux-I sequence checks for local_sink which isn't populated on MST links [HOW] Leave disable aux-i delay as 0 for MST cases Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler Reviewed-by: George Shen Reviewed-by: Aric Cyr Acked-by: Rodrigo Siqueira Signed-off-by: Michael Strauss Signed-off-by: Alex Deucher

drm/amd/display: Convert Delaying Aux-I Disable To Monitor Patch

2023-04-24T22:32:13Z

[WHY] 32ms delay was added to resolve issue with a specific sink, however this same delay also introduces erroneous link training failures with certain sink devices. [HOW] Only apply the 32ms delay for offending devices instead of globally. Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Michael Strauss Signed-off-by: Alex Deucher

drm/amd/display: Apply correct panel mode when reinitializing hardware

2023-04-18T20:28:53Z

[Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo Signed-off-by: Michael Mityushkin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher