<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dsc, branch linux-6.5.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.5.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.5.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2023-06-09T14:38:37Z</updated>
<entry>
<title>drm/amd/display: drop redundant memset() in get_available_dsc_slices()</title>
<updated>2023-06-09T14:38:37Z</updated>
<author>
<name>Hamza Mahfooz</name>
</author>
<published>2023-05-17T17:31:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=48dd83c0fb6c68742f7fefca907036942dd358be'/>
<id>urn:sha1:48dd83c0fb6c68742f7fefca907036942dd358be</id>
<content type='text'>
get_available_dsc_slices() returns the number of indices set, and all of
the users of get_available_dsc_slices() don't cross the returned bound
when iterating over available_slices[]. So, the memset() in
get_available_dsc_slices() is redundant and can be dropped.

Fixes: 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)")
Reported-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DSC policy override when ODM combine is forced</title>
<updated>2023-04-18T20:28:52Z</updated>
<author>
<name>Nasir Osman</name>
</author>
<published>2023-03-30T19:08:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6bfe9a23a8d6c7292d520747859a515fd429518d'/>
<id>urn:sha1:6bfe9a23a8d6c7292d520747859a515fd429518d</id>
<content type='text'>
[why]
When we force ODM combine with DSC, we lose several
8 bit and 10 bit modes in validation and thus
not able to use HDR. This is due to the number of
horizontal slices used in DSC not properly being
accounted for currently when 2:1 ODM Combine is forced.

[how]
Enforce at least two horizontal slices are used for DSC when
ODM combine is forced.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Nasir Osman &lt;nasir.osman@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: convert link.h functions to function pointer style</title>
<updated>2023-03-14T19:35:03Z</updated>
<author>
<name>Wenjing Liu</name>
</author>
<published>2023-02-23T22:04:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=98ce7d32e2154a6676d4dc7e6877af68cebf8832'/>
<id>urn:sha1:98ce7d32e2154a6676d4dc7e6877af68cebf8832</id>
<content type='text'>
[Why &amp; How]
All dc subcomponents should call another dc component via function pointers
stored in a component structure. This is part of dc coding convention since
the beginning. The reason behind this is to improve encapsulation and
polymorphism. The function contract is extracted into a single link service
structure defined in link.h header file and implemented only in link_factory.c instead
of spreading across multiple files in link component file structure.

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rename DCN config to FP</title>
<updated>2023-03-07T19:22:40Z</updated>
<author>
<name>Harry Wentland</name>
</author>
<published>2023-02-14T19:14:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4652ae7a51b78d7607c247228ac2a14fa0088bbf'/>
<id>urn:sha1:4652ae7a51b78d7607c247228ac2a14fa0088bbf</id>
<content type='text'>
[Why &amp; How]
The only reason we have the DCN config is for
floating point support. Rename it to make that
clear and (hopefully) avoid misuse of the config
in the future.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Build DSC without DCN config</title>
<updated>2023-03-07T19:22:40Z</updated>
<author>
<name>Harry Wentland</name>
</author>
<published>2023-02-13T20:29:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=84c03df58d8bbf77feb2f199f10dbe8f7f72c782'/>
<id>urn:sha1:84c03df58d8bbf77feb2f199f10dbe8f7f72c782</id>
<content type='text'>
[Why &amp; How]
DSC needs DCN but we are trying reduce the usage of the
DCN flag. It's easier to build the DSC code sprinkled
around DC core and the DMs and just guard the place where
DSC uses floating point code.

Since DSC is never enabled on non-DCN ASICs this won't
have any effect.

Reviewed-by: Hamza Mahfooz &lt;Hamza.Mahfooz@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix typo in dc_dsc_config_options structure</title>
<updated>2023-03-07T19:22:39Z</updated>
<author>
<name>Mike Hsieh</name>
</author>
<published>2023-02-20T03:48:26Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ab487ea8910d2a84f851cb87f2cb49adcb5b774b'/>
<id>urn:sha1:ab487ea8910d2a84f851cb87f2cb49adcb5b774b</id>
<content type='text'>
[WHY]
There is a typo in dc_dsc_config_options structure

[HOW]
Fix the typo

Reviewed-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Mike Hsieh &lt;Mike.Hsieh@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add height granularity limitation for dsc slice height calculation</title>
<updated>2023-03-07T19:22:39Z</updated>
<author>
<name>Mike Hsieh</name>
</author>
<published>2023-01-10T02:52:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=de534c1cb0313a070f45938a53b53927cd34e5b9'/>
<id>urn:sha1:de534c1cb0313a070f45938a53b53927cd34e5b9</id>
<content type='text'>
[WHY]
eDP add new limitation for Y granularity for selected update feature.
DSC does not include this limitation while calculating slice height.

[HOW]
Add new limitation while looking for DSC slice height.

Reviewed-by: Cruise Hung &lt;Cruise.Hung@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Mike Hsieh &lt;Mike.Hsieh@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add rc_params_override option in dc_dsc_config</title>
<updated>2023-01-31T19:00:51Z</updated>
<author>
<name>Wenjing Liu</name>
</author>
<published>2023-01-13T21:07:10Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=0a31efb4d606884d1ed17d5df64e9d02f50a0713'/>
<id>urn:sha1:0a31efb4d606884d1ed17d5df64e9d02f50a0713</id>
<content type='text'>
[why]
Current RC params are based on VESA recommended configurations.
Some DSC sink may prefer non standard rc params values due to
hardware limitations. To support those DSC sink we will allow DM to
optionally pass rc_params_ovrd in dc_dsc_config so DC will override
the default VESA recommended configurations.

Reviewed-by: Martin Leung &lt;Martin.Leung@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Fix spelling typo in comments</title>
<updated>2022-06-03T20:43:36Z</updated>
<author>
<name>pengfuyuan</name>
</author>
<published>2022-05-26T09:29:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=faf26f2b12e1e03956f7e628183e422d94713e4b'/>
<id>urn:sha1:faf26f2b12e1e03956f7e628183e422d94713e4b</id>
<content type='text'>
Fix spelling typo in comments.

Reported-by: k2ci &lt;kernel-bot@kylinos.cn&gt;
Signed-off-by: pengfuyuan &lt;pengfuyuan@kylinos.cn&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/display: Move DSC header and helpers into display-helper module</title>
<updated>2022-04-25T09:19:36Z</updated>
<author>
<name>Thomas Zimmermann</name>
</author>
<published>2022-04-21T07:31:05Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2a64b147350f5b28f6b41873fcb453aaebea01c3'/>
<id>urn:sha1:2a64b147350f5b28f6b41873fcb453aaebea01c3</id>
<content type='text'>
DSC is the Display Stream Compression standard for DisplayPort. Move
the DSC code into display/ and split the header into files for protocol
core and DRM helpers. Adapt all users of the code. No functional
changes.

To avoid the proliferation of Kconfig options, DSC is part of DRM's
support for DisplayPort. If necessary, a new option could make DSC an
independent feature.

Signed-off-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
Reviewed-by: Javier Martinez Canillas &lt;javierm@redhat.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-6-tzimmermann@suse.de
</content>
</entry>
</feed>
