kernel.git/drivers/gpu/drm/amd/display/dc/dsc, branch linux-6.17.y

drm/amd/display: Consider sink max slice width limitation for dsc

2025-11-13T20:37:08Z

[ Upstream commit 6b34e7ed4ba583ee77032a4c850ff97ba16ad870 ] [WHY&HOW] The sink max slice width limitation should be considered for DSC, but was removed in "refactor DSC cap calculations". This patch adds it back and takes the valid minimum between the sink and source. Signed-off-by: Dillon Varone Signed-off-by: Aurabindo Pillai Reviewed-by: Wenjing Liu Tested-by: Dan Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix divide by zero when calculating min ODM factor

2025-07-28T20:24:05Z

[WHY&HOW] If the debug option is set to disable_dsc the max slice width and/or dispclk can be zero. This causes a divide by zero when calculating the min ODM combine factor. Add a check to ensure they are valid first. Reviewed-by: Wenjing Liu Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd/display: Refactor DSC cap calculations

2025-07-15T18:07:51Z

[WHY] DSC block level should only be responsible for reporting single DSC instance capabilities. Factoring in ODM combine requirements should be handled in dc_dsc.c. Both components should acquire clocks from clk_mgr to determine throughput capabilities instead of relying on hard coded values as these can differ by SoC and SKU. [HOW] 1) Add dsc_get_single_enc_caps to acquire single DSC instance capabilities (replacing dsc_get_enc_caps), factoring in DSCCLK 2) add build_dsc_enc_caps to combine single DSC instance capabilities 3) account for max pixel rate per pipe (DISPCLK) when calculating minimum slice count Reviewed-by: Wenjing Liu Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Make dcn401_initialize_min_clocks() available to other compilation units

2025-07-15T18:07:51Z

[Why & How] Expose dcn401_initialize_min_clocks() for future use and add additional check for IP register. Reviewed-by: Nevenko Stupar Signed-off-by: Karthi Kandasamy Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: prepare for new platform

2025-06-30T15:58:44Z

[Why & How] Expose some function for new platform use Reviewed-by: Nevenko Stupar Signed-off-by: Karthi Kandasamy Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.

2025-05-05T16:54:18Z

[Why] Previously the 'dsc_bits_per_comp' enumeration was defined in individual .c files, making it unavailable for other files that may need it. [How] The 'dsc_bits_per_comp' enumeration has been relocated to a common header file. Reviewed-by: Mounika Adhuri Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Allow reuse of of DCN4x code

2025-02-13T02:03:01Z

Remove the static qualifier to make it available for code sharing with other components. Reviewed-by: Charlene Liu Signed-off-by: Dmytro Signed-off-by: Charlene Liu Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add Interface to Dump DSC Caps from dm

2025-01-06T19:44:27Z

No common dsc params found between encoder and decoder is one of the reason that could prevent dsc from properly enabled. Dump the params to a specific timing to help locate possible invalid dsc params in either encoder or decoder side. Reviewed-by: Aurabindo Pillai Signed-off-by: Fangzhi Zuo Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: remove redundant is_dsc_possible check

2024-11-20T14:38:16Z

Since is_dsc_possible is already checked just above, there's no need to check it again before filling out the DSC settings. Signed-off-by: Bhavin Sharma Signed-off-by: Alex Deucher

drm/amd/display: Add HDMI DSC native YCbCr422 support

2024-09-18T20:15:07Z

[WHY && HOW] For some HDMI OVT timing, YCbCr422 encoding fails at the DSC bandwidth check. The root cause is our DSC policy for timing doesn't account for HDMI YCbCr422 native support. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Chris Park Signed-off-by: Leo Ma Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher