<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dsc, branch linux-6.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.10.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.10.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2024-10-04T14:33:28Z</updated>
<entry>
<title>drm/amd/display: Add HDMI DSC native YCbCr422 support</title>
<updated>2024-10-04T14:33:28Z</updated>
<author>
<name>Leo Ma</name>
</author>
<published>2024-08-19T17:25:27Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fbf3cff7c0586ecb1153e9bb8230929c22b317d9'/>
<id>urn:sha1:fbf3cff7c0586ecb1153e9bb8230929c22b317d9</id>
<content type='text'>
commit 07bfa9cdbf3cd2daadfaaba0601f126f45951ffa upstream.

[WHY &amp;&amp; HOW]
For some HDMI OVT timing, YCbCr422 encoding fails at the DSC
bandwidth check. The root cause is our DSC policy for timing
doesn't account for HDMI YCbCr422 native support.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Signed-off-by: Leo Ma &lt;hanghong.ma@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix division by zero in setup_dsc_config</title>
<updated>2024-04-26T21:22:40Z</updated>
<author>
<name>Jose Fernandez</name>
</author>
<published>2024-04-22T14:35:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=130afc8a886183a94cf6eab7d24f300014ff87ba'/>
<id>urn:sha1:130afc8a886183a94cf6eab7d24f300014ff87ba</id>
<content type='text'>
When slice_height is 0, the division by slice_height in the calculation
of the number of slices will cause a division by zero driver crash. This
leaves the kernel in a state that requires a reboot. This patch adds a
check to avoid the division by zero.

The stack trace below is for the 6.8.4 Kernel. I reproduced the issue on
a Z16 Gen 2 Lenovo Thinkpad with a Apple Studio Display monitor
connected via Thunderbolt. The amdgpu driver crashed with this exception
when I rebooted the system with the monitor connected.

kernel: ? die (arch/x86/kernel/dumpstack.c:421 arch/x86/kernel/dumpstack.c:434 arch/x86/kernel/dumpstack.c:447)
kernel: ? do_trap (arch/x86/kernel/traps.c:113 arch/x86/kernel/traps.c:154)
kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu
kernel: ? do_error_trap (./arch/x86/include/asm/traps.h:58 arch/x86/kernel/traps.c:175)
kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu
kernel: ? exc_divide_error (arch/x86/kernel/traps.c:194 (discriminator 2))
kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu
kernel: ? asm_exc_divide_error (./arch/x86/include/asm/idtentry.h:548)
kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu
kernel: dc_dsc_compute_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1109) amdgpu

After applying this patch, the driver no longer crashes when the monitor
is connected and the system is rebooted. I believe this is the same
issue reported for 3113.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Jose Fernandez &lt;josef@netflix.com&gt;
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3113
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update DSC compute parameter calculation</title>
<updated>2024-04-10T02:05:58Z</updated>
<author>
<name>Rodrigo Siqueira</name>
</author>
<published>2024-03-22T00:20:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ffa6d7ab1b4acae9cab8adfd0ad340c74a8589c5'/>
<id>urn:sha1:ffa6d7ab1b4acae9cab8adfd0ad340c74a8589c5</id>
<content type='text'>
Adjust bytes per pixel calculation to use div_u64.

Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix compiler warnings on high compiler warning levels</title>
<updated>2024-04-10T02:05:04Z</updated>
<author>
<name>Aric Cyr</name>
</author>
<published>2024-03-12T18:40:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=aece2094e34e602f37403dda028f464bb41da50c'/>
<id>urn:sha1:aece2094e34e602f37403dda028f464bb41da50c</id>
<content type='text'>
[why]
Enabling higher compiler warning levels results in many issues that can
be trivially resolved as well as some potentially critical issues.

[how]
Fix all compiler warnings found with various compilers and higher
warning levels.  Primarily, potentially uninitialized variables and
unreachable code.

Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix timing bandwidth calculation for HDMI</title>
<updated>2024-01-22T22:13:26Z</updated>
<author>
<name>Leo (Hanghong) Ma</name>
</author>
<published>2024-01-04T18:29:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c597479f27b6b96c61c70cb25b5e1a4f9ea4c7f7'/>
<id>urn:sha1:c597479f27b6b96c61c70cb25b5e1a4f9ea4c7f7</id>
<content type='text'>
[Why &amp;&amp; How]
The current bandwidth calculation for timing doesn't account for
certain HDMI modes overhead which leads to DSC can't be enabled.
Add support to calculate the actual bandwidth for these HDMI modes.

Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Leo (Hanghong) Ma &lt;hanghong.ma@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DSC granular throughput adjustment</title>
<updated>2023-11-29T21:49:23Z</updated>
<author>
<name>Ilya Bakoulin</name>
</author>
<published>2023-11-16T20:28:53Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5290ed0a8b261115fe4965a6d95a642b0742d159'/>
<id>urn:sha1:5290ed0a8b261115fe4965a6d95a642b0742d159</id>
<content type='text'>
[Why/How]
Update DSC DPCD parsing to take granular throughput adjustment into
consideration.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Ilya Bakoulin &lt;ilya.bakoulin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor DSC into component folder</title>
<updated>2023-11-29T21:48:59Z</updated>
<author>
<name>Bhuvana Chandra Pinninti</name>
</author>
<published>2023-10-18T13:46:17Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6c22fb07e0c2935d97a86509f16f755ab895f2c8'/>
<id>urn:sha1:6c22fb07e0c2935d97a86509f16f755ab895f2c8</id>
<content type='text'>
[why]

To refactor DSC and make DSC files unit testable.

[how]

moved the dcnxx_dsc.c and .h files
into corresponding dcn folders inside
the dsc and cleared the linkage errors.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Bhuvana Chandra Pinninti &lt;bhuvanachandra.pinninti@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Allow 16 max_slices for DP2 DSC</title>
<updated>2023-11-07T16:17:03Z</updated>
<author>
<name>Fangzhi Zuo</name>
</author>
<published>2023-10-18T13:38:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8df0d7d33a58d9394bd1240205e393d5f2bab6c7'/>
<id>urn:sha1:8df0d7d33a58d9394bd1240205e393d5f2bab6c7</id>
<content type='text'>
Enable 12 and 16 max_slices for DP2 DSC

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Acked-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add link encoding to timing BW calculation parameters</title>
<updated>2023-07-18T15:15:51Z</updated>
<author>
<name>George Shen</name>
</author>
<published>2023-06-17T02:35:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=63c0bf99c1d020a744eff286d65b33e2960d9d6b'/>
<id>urn:sha1:63c0bf99c1d020a744eff286d65b33e2960d9d6b</id>
<content type='text'>
[Why]
There certain cases where the timing BW is dependent on the type of link
encoding in use. Thus to calculate the correct BW required for a given
timing, the link encoding should be added as a parameter.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Acked-by: Alan Liu &lt;haoping.liu@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add stream overhead in BW calculations for 128b/132b</title>
<updated>2023-07-18T15:15:45Z</updated>
<author>
<name>George Shen</name>
</author>
<published>2023-04-11T00:00:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=974764180838516f80a13257da67a1ec6afb87d4'/>
<id>urn:sha1:974764180838516f80a13257da67a1ec6afb87d4</id>
<content type='text'>
[Why]
Current BW calculations do not account for the additional padding added
for uncompressed pixel-to-symbol packing.

This results in X.Y being too low for 128b/132b SST streams in certain
scenarios. If X.Y is too low, end user can observe image corruption.

[How]
Add function to calculate stream overhead to timing BW calculation for
128b/132b SST cases.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Acked-by: Alan Liu &lt;haoping.liu@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
