kernel.git/drivers/gpu/drm/amd/display/dc/dsc, branch linux-5.3.y

drm/amd/display: readd -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines

2019-10-01T06:24:45Z

commit 0f0727d971f6fdf8f1077180d495ddb9928f0c8b upstream. arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn on SSE2 to support emitting double precision floating point instructions rather than calls to non-existent (usually available from gcc_s or compiler_rt) floating point helper routines for Clang. This was originally landed in: commit 10117450735c ("drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines") but reverted in: commit 193392ed9f69 ("Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"") due to bugreports from GCC builds. Add guards to only do so for Clang. Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487 Link: https://github.com/ClangBuiltLinux/linux/issues/327 Suggested-by: Sedat Dilek Suggested-by: Sami Tolvanen Signed-off-by: Nick Desaulniers Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Set one 4:2:0-related PPS field as recommended by DSC spec

2019-07-18T19:17:18Z

[why] 'second_line_offset_adj' was mistakenly left at zero, even though DSC spec v1.2a recommends setting this field to 512 for 4:2:0. [how] Set 'second_line_offset_adj' to 512 for 4:2:0 and leave at zero otherwise Signed-off-by: Nikola Cornij Reviewed-by: Eric Bernstein Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Support clang option for stack alignment

2019-07-16T18:02:39Z

As previously fixed for dml in commit 4769278e5c7f ("amdgpu/dc/dml: Support clang option for stack alignment") and calcs in commit cc32ad8f559c ("amdgpu/dc/calcs: Support clang option for stack alignment"), dcn20 uses an option that is not available with clang: clang: error: unknown argument: '-mpreferred-stack-boundary=4' scripts/Makefile.build:281: recipe for target 'drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.o' failed Use the same trick that we have in the other two files. Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher

drm/amd/display: fix a couple of spelling mistakes

2019-06-27T16:22:57Z

There are a couple of spelling mistakes in dm_error messages and a comment. Fix these. Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher

drm/amd/display: update dsc max_target_bpp to 16 bpp

2019-06-22T14:34:13Z

[why] According to the latest specs, the max_target bpp sink can support is 16 bpp. [how] update dsc max_target_bpp to 16 Signed-off-by: Wenjing Liu Reviewed-by: Jun Lei Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy

2019-06-22T14:34:13Z

[why] Current policy assumes virtual DPCD peer device as an individual MST branch device with 1 input and 1 output. However this is only true for virtual DP-to-DP peer device. In general there are three types of virtual DP peer devices. 1. Sink peer device with virtual DPCD. 2. Virtual DP-to-DP Peer device with virtual DPCD. 3. Virtual DP-to-HDMI Protocol Converter Peer Device with Virtual DPCD. So we should break the assumption and handle all three types. [how] DP-to-DP peer device will have virtual DPCD cap upstream. Sink peer device will have virtual DPCD on the logical port. Dp to HDMI protocol converter peer device will have virtual DPCD on its converter port. For DSC capable Synaptics non VGA port we workaround by enumerating a virutal DPCD peer device on its upstream even if it doesn't have one. Signed-off-by: Wenjing Liu Reviewed-by: Jun Lei Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: fix a potential issue in DSC logic

2019-06-22T14:34:12Z

[why] In compute dsc bandwidth range there is an uninitialized variable [how] Initialize the variable to the correct value. Signed-off-by: Wenjing Liu Reviewed-by: Nikola Cornij Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Add support for extended DSC DPCD caps

2019-06-22T14:34:11Z

[why] A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order to give DSC branch decoders a chance to expose their maximum throughput and maximum line width limitations. Signed-off-by: Nikola Cornij Reviewed-by: Wenjing Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Add 170Mpix/sec DSC throughput support

2019-06-22T14:34:11Z

[why] It was missing, although defined in DP spec [how] - Add handling of this value to DSC code - Also remove unused file dsc_helpers.c Signed-off-by: Nikola Cornij Reviewed-by: Joshua Aberback Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Consider DSC target bpp precision when calculating DSC target bpp

2019-06-22T14:34:10Z

[why] DSC target bpp precision is a decoder DPCD and an AMD encoder capability. It must be taken into account when calculating target bitrate. [how] Add a DC DSC function that does this calculation. Signed-off-by: Nikola Cornij Reviewed-by: Wenjing Liu Acked-by: Leo Li Acked-by: Hawking Zhang Acked-by: Tony Cheng Signed-off-by: Alex Deucher