kernel.git/drivers/gpu/drm/amd/display/dc/dsc, branch linux-5.14.y

drm/amd/display: add dsc stream overhead for dp only

2021-05-10T22:06:44Z

[why] Based on hardware team recommendation this additional dsc overhead is only required for DP DSC. [how] Add a check for is_dp and only apply the overhead if this flag is set. Signed-off-by: Wenjing Liu Reviewed-by: Chris Park Acked-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: take max dsc stream bandwidth overhead into account

2021-04-29T03:35:50Z

[why] As hardware team suggested that we need to add a max dsc bw overhead into existing stream bandwidth when DSC is used. The formula as below: max_dsc_bw_overhead = v_addressable * slice_count * 256 bit * pixel clock / v_total / h_total effective stream bandwidth = pixel clock * bpp stream bandwidth = effective stream bandwidth + dsc stream overhead Signed-off-by: Wenjing Liu Reviewed-by: Eric Bernstein Acked-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations

2021-03-24T03:32:31Z

[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to calculate stream bandwidth from timing. [How?] Fix code to work with 16ths instead of whole bits for dsc bpp. Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit. Use dc function to calculate bandwidth from timing, and make dsc bw calculation a part of dsc.c. Tested-by: Daniel Wheeler Signed-off-by: Dillon Varone Reviewed-by: Wenjing Liu Acked-by: Solomon Chiu Signed-off-by: Alex Deucher

drm/amd/display: revert support for DID2.0 dsc passthrough

2021-02-09T20:31:07Z

3x4K60 displays over MST with DSC enabled was not able to light up due to this patch. Signed-off-by: Jun Lei Reviewed-by: Anthony Koo Acked-by: Anson Jacob Signed-off-by: Alex Deucher

drm/amd/display: implement support for DID2.0 dsc passthrough

2021-02-02T17:10:48Z

[Why] Some panels contain active converters (e.g. DP to MIPI) which only support restricted DSC configurations. DID2.0 adds support for such displays to explicitly define per timing BPP restrictions on DSC. Ignoring these restrictions leads to blackscreen. [How] Add parsing in DID2.0 parser to get this bpp info. Add support in DSC module to constraint target bpp based on this info. Signed-off-by: Jun Lei Reviewed-by: Wenjing Liu Acked-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amdgpu/display: drop DCN support for aarch64

2021-01-05T16:35:53Z

From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon Reported-by: Ard Biesheuvel Signed-off-by: Alex Deucher

drm/amd/display: Fix compilation error

2020-11-02T20:29:33Z

[Why] The C standard does not specify whether an enum is signed or unsigned. In the function prototype, one of the argument is defined as an enum but its declaration was unit32_t. Fix this by changing the function argument to enum in the declaration. Signed-off-by: Tao.Huang Signed-off-by: Florin Iucha Reviewed-by: Dmytro Laktyushkin Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher

drm/amd/display: Add an option to limit max DSC target bpp per sink

2020-10-26T17:29:39Z

[Why] Can be used for debug purposes [How] Add max target bpp override field and related handling Signed-off-by: Nikola Cornij Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: Mask DPCD field to avoid reading unsupported field value

2020-08-17T18:09:06Z

[Why] DSC will be disabled if DPCD 0006F[6:3] is set to a non-zero value because bits 6:3 are not currently supported. When 6:3 is populated, an unsupported INCREMENT OF bits_per_pixel value is read (DPCD 0006F[2:0]) [How] Mask the INCREMENT OF bits_per_pixel field so that values in the unsupported field are ignored. Signed-off-by: Jaehyun Chung Reviewed-by: Wenjing Liu Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Fix DSC force enable on SST

2020-08-17T18:08:34Z

[why] Previously when force enabling DSC on SST display we unknowingly supressed lane count, which caused DSC to be enabled automatically. [how] By adding an additional flag to force enable DSC in dc_dsc.c DSC can always be enabled with debugfs dsc_clock_en forced to 1 Cc: stable@vger.kernel.org Signed-off-by: Eryk Brol Signed-off-by: Mikita Lipski Reviewed-by: Wenjing Liu Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher