kernel.git/drivers/gpu/drm/amd/display/dc/dpp, branch linux-6.16.y

drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PG

2025-09-09T17:02:33Z

commit 3ebf766c35464ebdeefb6068246267147503dc04 upstream. [Why&How] ON DCN314, clearing DPP SW structure without power gating it can cause a double cursor in full screen with non-native scaling. A W/A that clears CURSOR0_CONTROL cursor_enable flag if dcn10_plane_atomic_power_down is called and DPP power gating is disabled. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168 Reviewed-by: Sun peng (Leo) Li Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher (cherry picked from commit 645f74f1dc119dad5a2c7bbc05cc315e76883011) Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

Revert "drm/amd/display: Hardware cursor changes color when switched to software cursor"

2025-05-14T15:27:09Z

This reverts commit 272e6aab14bbf98d7a06b2b1cd6308a02d4a10a1. Applying degamma curve to the cursor by default breaks Linux userspace expectation. On Linux, AMD display manager enables cursor degamma ROM just for implict sRGB on HW versions where degamma is split into two blocks: degamma ROM for pre-defined TFs and `gamma correction` for user/custom curves, and degamma ROM settings doesn't apply to cursor plane. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1513 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2803 Reported-by: Michel Dänzer Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4144 Signed-off-by: Melissa Wen Reviewed-by: Alex Hung Signed-off-by: Alex Deucher

drm/amd/display: Update IPS sequential_ono requirement checks

2025-05-05T16:54:12Z

[why & how] ASICs that require special RCG/PG programming are determined based on hw_internal_rev. Update these checks to properly include all such ASICs. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove double checks for `debug.enable_mem_low_power.bits.cm`

2025-04-07T22:01:07Z

[Why] A variety of the 3DLUT handling functions check `debug.enable_mem_low_power.bits.cm` both in the caller and function. This is unnecessary overhead. [How] For each of them reduce to just checking just in caller or function. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: handle max_downscale_src_width fail check

2025-02-25T16:45:11Z

[WHY] If max_downscale_src_width check fails, we exit early from TAP calculation and left a NULL value to the scaling data structure to cause the zero divide in the DML validation. [HOW] Call set default TAP calculation before early exit in get_optimal_number_of_taps due to max downscale limit exceed. Reviewed-by: Samson Tam Signed-off-by: Yihan Zhu Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Refactor DCN4x and related code

2025-02-25T16:44:02Z

[why & how] Refactor existing code related to DCN4x for better code sharing with other modules. Reviewed-by: Charlene Liu Signed-off-by: Swapnil Patel Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Move SPL to a new path

2025-02-13T02:03:01Z

[WHY & HOW] - Move SPL from dc/spl to dc/sspl - Update build files and header paths - Remove dc/spl files Reviewed-by: George Zhang Signed-off-by: Samson Tam Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Optimize cursor position updates

2025-01-24T14:56:28Z

[why] Updating the cursor enablement register can be a slow operation and accumulates when high polling rate cursors cause frequent updates asynchronously to the cursor position. [how] Since the cursor enable bit is cached there is no need to update the enablement register if there is no change to it. This removes the read-modify-write from the cursor position programming path in HUBP and DPP, leaving only the register writes. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Sung Lee Signed-off-by: Aric Cyr Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add hubp cache reset when powergating

2025-01-24T14:56:22Z

[Why] When HUBP is power gated, the SW state can get out of sync with the hardware state causing cursor to not be programmed correctly. [How] Similar to DPP, add a HUBP reset function which is called wherever HUBP is initialized or powergated. This function will clear the cursor position and attribute cache allowing for proper programming when the HUBP is brought back up. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Sung Lee Signed-off-by: Aric Cyr Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: store sharpness 1dlut table in dscl_prog_data

2024-10-28T20:37:02Z

[Why] Previously dscl_prog_data stored pointer to sharpness 1dlut table. SPL had four pre-generated tables, one for each setup. This allowed us to minimize number of times we had to recalculate table when switching between setups. However, with dual display, this becomes an issue because for a given setup, we could have a different per app sharpness value than the global sharpness value. So the pre-generated table will change but both displays may point to the same table and one of them will have the wrong sharpness setting. [How] Store the sharpness 1dlut table in dscl_prog_data. This ensures that each display can have its own sharpness setting. Reviewed-by: Ilya Bakoulin Signed-off-by: Samson Tam Signed-off-by: Tom Chung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher