<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dml, branch linux-6.5.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.5.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.5.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2023-09-23T09:14:25Z</updated>
<entry>
<title>drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN314</title>
<updated>2023-09-23T09:14:25Z</updated>
<author>
<name>Leo Chen</name>
</author>
<published>2023-07-27T02:44:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8e149d14a5e77d376b7098e0a3cfefdafc03681e'/>
<id>urn:sha1:8e149d14a5e77d376b7098e0a3cfefdafc03681e</id>
<content type='text'>
[ Upstream commit 4c6107a653ccf361cb1b6ba35d558a1a5e6e57ac ]

[Why &amp; How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN314 will resolve
intermittent corruptions issues.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Leo Chen &lt;sancchen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN31</title>
<updated>2023-09-23T09:14:25Z</updated>
<author>
<name>Leo Chen</name>
</author>
<published>2023-07-24T20:57:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5c1f969932714acbd172c13c8cd77c64b3e10cca'/>
<id>urn:sha1:5c1f969932714acbd172c13c8cd77c64b3e10cca</id>
<content type='text'>
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]

[Why &amp; How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Leo Chen &lt;sancchen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix underflow issue on 175hz timing</title>
<updated>2023-09-23T09:14:24Z</updated>
<author>
<name>Leo Ma</name>
</author>
<published>2023-07-06T20:17:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5f2374b65fe5138b1f7111f5c90eb7a61cceee8b'/>
<id>urn:sha1:5f2374b65fe5138b1f7111f5c90eb7a61cceee8b</id>
<content type='text'>
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]

[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.

[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Leo Ma &lt;hanghong.ma@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: limit the v_startup workaround to ASICs older than DCN3.1</title>
<updated>2023-09-19T10:30:25Z</updated>
<author>
<name>Hamza Mahfooz</name>
</author>
<published>2023-08-31T19:22:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f5da0ee56e5f103c91cb3601fa945d52c82dd715'/>
<id>urn:sha1:f5da0ee56e5f103c91cb3601fa945d52c82dd715</id>
<content type='text'>
commit 47428f4b638d3b3264a2efa1a567b0bbddbb6107 upstream.

Since, calling dcn20_adjust_freesync_v_startup() on DCN3.1+ ASICs
can cause the display to flicker and underflow to occur, we shouldn't
call it for them. So, ensure that the DCN version is less than
DCN_VERSION_3_1 before calling dcn20_adjust_freesync_v_startup().

Cc: stable@vger.kernel.org
Reviewed-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amd/display: Remove v_startup workaround for dcn3+"</title>
<updated>2023-09-19T10:30:25Z</updated>
<author>
<name>Hamza Mahfooz</name>
</author>
<published>2023-08-31T19:17:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cc502fe191074c208cb9fe32ce5bda29c720a7b1'/>
<id>urn:sha1:cc502fe191074c208cb9fe32ce5bda29c720a7b1</id>
<content type='text'>
commit a81de4a22bbe3183b7f0d6f13f592b8f5b5a3c18 upstream.

This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.

We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs. Otherwise, it can cause DP to HDMI 2.1 PCONs to fail to light up.

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809
Reviewed-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Prevent vtotal from being set to 0</title>
<updated>2023-07-18T18:40:56Z</updated>
<author>
<name>Daniel Miess</name>
</author>
<published>2023-06-22T12:11:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2a9482e55968ed7368afaa9c2133404069117320'/>
<id>urn:sha1:2a9482e55968ed7368afaa9c2133404069117320</id>
<content type='text'>
[Why]
In dcn314 DML the destination pipe vtotal was being set
to the crtc adjustment vtotal_min value even in cases
where that value is 0.

[How]
Only set vtotal to the crtc adjustment vtotal_min value
in cases where the value is non-zero.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Alan Liu &lt;haoping.liu@amd.com&gt;
Signed-off-by: Daniel Miess &lt;daniel.miess@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove asserts</title>
<updated>2023-06-30T17:11:35Z</updated>
<author>
<name>Hong-lu Cheng</name>
</author>
<published>2023-06-12T17:48:53Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2aafcdd6a68f30c85ba6a9600e8a7447c0228e51'/>
<id>urn:sha1:2aafcdd6a68f30c85ba6a9600e8a7447c0228e51</id>
<content type='text'>
[why]
Endless assert caused by LinesInDETChroma=0.

[how]
Don't floor for LinesInDETChroma=0

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Hong-lu Cheng &lt;hong-lu.cheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Disable DC Mode Capping On DCN321</title>
<updated>2023-06-23T19:43:32Z</updated>
<author>
<name>Austin Zheng</name>
</author>
<published>2023-06-07T16:20:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2bf0ce3bec8b22e4bac828aeaeade15884fa0f5c'/>
<id>urn:sha1:2bf0ce3bec8b22e4bac828aeaeade15884fa0f5c</id>
<content type='text'>
Why:
Limiting clocks to DC mode max results in some
display modes to no longer be supported

How:
Disable the path that limits the clock values

Fixes: 3b718dcaf163 ("drm/amd/display: Filter out AC mode frequencies on DC mode systems")
Reviewed-by: Martin Leung &lt;martin.leung@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add Clock Table Entry With Max DC Values</title>
<updated>2023-06-23T19:40:50Z</updated>
<author>
<name>Austin Zheng</name>
</author>
<published>2023-06-05T22:17:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c5f78ea8d768ce6f4471b0921728c2bd2dd95d93'/>
<id>urn:sha1:c5f78ea8d768ce6f4471b0921728c2bd2dd95d93</id>
<content type='text'>
Why:
Certain display configs resulted in underflow

How:
Add an entry containing all max DC clock timings

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Partially revert "drm/amd/display: Fix possible underflow for displays with large vblank"</title>
<updated>2023-06-23T19:39:15Z</updated>
<author>
<name>Daniel Miess</name>
</author>
<published>2023-05-31T15:47:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a99a4ff6ef205d125002fc7e0857074e4e6597b6'/>
<id>urn:sha1:a99a4ff6ef205d125002fc7e0857074e4e6597b6</id>
<content type='text'>
This partially reverts commit de231189e7bf ("drm/amd/display: Fix
possible underflow for displays with large vblank").

[Why]
The increased value of VBlankNomDefaultUS causes underflow at the
desktop of an IP KVM setup

[How]
Change the value from 800 back to 668

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Daniel Miess &lt;daniel.miess@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
