<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dml, branch linux-6.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2025-05-29T09:13:26Z</updated>
<entry>
<title>drm/amd/display: pass calculated dram_speed_mts to dml2</title>
<updated>2025-05-29T09:13:26Z</updated>
<author>
<name>Charlene Liu</name>
</author>
<published>2025-01-13T16:57:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=433de1f2e3e42d30ab3bc968f5e9c405e2b5ae04'/>
<id>urn:sha1:433de1f2e3e42d30ab3bc968f5e9c405e2b5ae04</id>
<content type='text'>
[ Upstream commit b40d022ec06ade9f6c809091dc188422a0f0946d ]

[why]
currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts.
for apu, this depends on wck_ratio.

change to pass the already calculated dram_speed_mts from fpu to dml2.

v2: use existing calculation of dram_speed_mts for now to avoid regression

Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Reviewed-by: Roman Li &lt;Roman.Li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amd/display: Request HW cursor on DCN3.2 with SubVP"</title>
<updated>2025-05-29T09:13:16Z</updated>
<author>
<name>Leo Zeng</name>
</author>
<published>2025-01-31T16:46:52Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d5a6fe32ee1d66be3cec0075a081b3ba61f5f8ed'/>
<id>urn:sha1:d5a6fe32ee1d66be3cec0075a081b3ba61f5f8ed</id>
<content type='text'>
[ Upstream commit 8ae6dfc0b61b170cf13832d4cfe2a0c744e621a7 ]

This reverts commit 13437c91606c9232c747475e202fe3827cd53264.

Reason to revert: idle power regression found in testing.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Leo Zeng &lt;Leo.Zeng@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Request HW cursor on DCN3.2 with SubVP</title>
<updated>2025-05-29T09:12:57Z</updated>
<author>
<name>Aric Cyr</name>
</author>
<published>2025-01-23T21:39:52Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cfbfa2c9f3d860b64321d6de7a02adc29df9b496'/>
<id>urn:sha1:cfbfa2c9f3d860b64321d6de7a02adc29df9b496</id>
<content type='text'>
[ Upstream commit b74f46f3ce1e5f6336645f1e9ff47c56d5dfdef1 ]

[why]
When SubVP is active the HW cursor size is limited to 64x64, and
anything larger will force composition which is bad for gaming on
DCN3.2 if the game uses a larger cursor.

[how]
If HW cursor is requested, typically by a fullscreen game, do not
enable SubVP so that up to 256x256 cursor sizes are available for
DCN3.2.

Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable urgent latency adjustment on DCN35</title>
<updated>2025-05-29T09:12:21Z</updated>
<author>
<name>Nicholas Susanto</name>
</author>
<published>2025-04-02T19:04:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=40a4242314ad45c6f0e681c12566edc9dbc66bde'/>
<id>urn:sha1:40a4242314ad45c6f0e681c12566edc9dbc66bde</id>
<content type='text'>
[ Upstream commit 756c85e4d0ddc497b4ad5b1f41ad54e838e06188 ]

[Why]

Urgent latency adjustment was disabled on DCN35 due to issues with P0
enablement on some platforms. Without urgent latency, underflows occur
when doing certain high timing configurations. After testing, we found
that reenabling urgent latency didn't reintroduce p0 support on multiple
platforms.

[How]

renable urgent latency on DCN35 and setting it to 3000 Mhz.

This reverts commit 3412860cc4c0c484f53f91b371483e6e4440c3e5.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Nicholas Susanto &lt;nsusanto@amd.com&gt;
Signed-off-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit cd74ce1f0cddffb3f36d0995d0f61e89f0010738)
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix type mismatch in CalculateDynamicMetadataParameters()</title>
<updated>2025-04-10T12:44:18Z</updated>
<author>
<name>Vitaliy Shevtsov</name>
</author>
<published>2025-02-26T20:28:51Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=19eabfdf5facba8098d2d39b705d13e9750e7ec3'/>
<id>urn:sha1:19eabfdf5facba8098d2d39b705d13e9750e7ec3</id>
<content type='text'>
[ Upstream commit c3c584c18c90a024a54716229809ba36424f9660 ]

There is a type mismatch between what CalculateDynamicMetadataParameters()
takes and what is passed to it. Currently this function accepts several
args as signed long but it's called with unsigned integers and integer. On
some systems where long is 32 bits and one of these unsigned int params is
greater than INT_MAX it may cause passing input params as negative values.

Fix this by changing these argument types from long to unsigned int and to
int respectively. Also this will align the function's definition with
similar functions in other dcn* drivers.

Found by Linux Verification Center (linuxtesting.org) with Svace.

Fixes: 6725a88f88a7 ("drm/amd/display: Add DCN3 DML")
Signed-off-by: Vitaliy Shevtsov &lt;v.shevtsov@mt-integration.ru&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Respect user's CONFIG_FRAME_WARN more for dml files</title>
<updated>2025-02-04T22:47:10Z</updated>
<author>
<name>Nathan Chancellor</name>
</author>
<published>2025-01-31T22:31:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=820ccf8cb2b145ab9fc12651f7f80339614fa46c'/>
<id>urn:sha1:820ccf8cb2b145ab9fc12651f7f80339614fa46c</id>
<content type='text'>
Currently, there are several files in drm/amd/display that aim to have a
higher -Wframe-larger-than value to avoid instances of that warning with
a lower value from the user's configuration. However, with the way that
it is currently implemented, it does not respect the user's request via
CONFIG_FRAME_WARN for a higher stack frame limit, which can cause pain
when new instances of the warning appear and break the build due to
CONFIG_WERROR.

Adjust the logic to switch from a hard coded -Wframe-larger-than value
to only using the value as a minimum clamp and deferring to the
requested value from CONFIG_FRAME_WARN if it is higher.

Suggested-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reported-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Closes: https://lore.kernel.org/2025013003-audience-opposing-7f95@gregkh/
Signed-off-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amd/display: Enable urgent latency adjustments for DCN35"</title>
<updated>2025-01-10T17:05:09Z</updated>
<author>
<name>Nicholas Susanto</name>
</author>
<published>2024-12-19T19:15:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c7ccfc0d4241a834c25a9a9e1e78b388b4445d23'/>
<id>urn:sha1:c7ccfc0d4241a834c25a9a9e1e78b388b4445d23</id>
<content type='text'>
Revert commit 284f141f5ce5 ("drm/amd/display: Enable urgent latency adjustments for DCN35")

[Why &amp; How]

Urgent latency increase caused  2.8K OLED monitor caused it to
block this panel support P0.

Reverting this change does not reintroduce the netflix corruption issue
which it fixed.

Fixes: 284f141f5ce5 ("drm/amd/display: Enable urgent latency adjustments for DCN35")
Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Nicholas Susanto &lt;Nicholas.Susanto@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add check for granularity in dml ceil/floor helpers</title>
<updated>2025-01-06T19:44:28Z</updated>
<author>
<name>Roman Li</name>
</author>
<published>2024-12-13T18:51:07Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f6e09701c3eb2ccb8cb0518e0b67f1c69742a4ec'/>
<id>urn:sha1:f6e09701c3eb2ccb8cb0518e0b67f1c69742a4ec</id>
<content type='text'>
[Why]
Wrapper functions for dcn_bw_ceil2() and dcn_bw_floor2()
should check for granularity is non zero to avoid assert and
divide-by-zero error in dcn_bw_ functions.

[How]
Add check for granularity 0.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add 6bpc RGB case for dcn32 output bpp calculations</title>
<updated>2025-01-06T19:44:28Z</updated>
<author>
<name>George Shen</name>
</author>
<published>2024-12-12T21:17:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=79a57f9479de9c6fc3a8c4f50e7c853a134f9b41'/>
<id>urn:sha1:79a57f9479de9c6fc3a8c4f50e7c853a134f9b41</id>
<content type='text'>
[Why]
Current DCN32 calculation doesn't consider RGB 6bpc for the DP case.
This results in an invalid output bpp being calculated when DSC is not
enabled in the configuration, failing the mode validation.

[How]
Add special case to handle 6bpc RGB in the output bpp calculation.

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: delete legacy code</title>
<updated>2024-12-18T17:19:57Z</updated>
<author>
<name>Shunlu Zhang</name>
</author>
<published>2024-11-14T00:21:40Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5b0766f2de9211395e1374ebc5173e0cb60b8fd7'/>
<id>urn:sha1:5b0766f2de9211395e1374ebc5173e0cb60b8fd7</id>
<content type='text'>
Delete unused code.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Signed-off-by: Shunlu Zhang &lt;Shunlu.Zhang@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
