kernel.git/drivers/gpu/drm/amd/display/dc/dml, branch linux-5.16.y

drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU.

2022-02-01T16:29:04Z

commit 25f1488bdbba63415239ff301fe61a8546140d9f upstream. Mirrors the logic for dcn30. Cue lots of WARNs and some kernel panics without this fix. Cc: stable@vger.kernel.org Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amdgpu/display: Remove t_srx_delay_us.

2022-02-01T16:29:04Z

commit 2a807341ed1074ab83638f2fab08dffaa373f6b8 upstream. Unused. Convert the divisions into asserts on the divisor, to debug why it is zero. The divide by zero is suspected of causing kernel panics. While I have no idea where the zero is coming from I think this patch is a positive either way. Cc: stable@vger.kernel.org Reviewed-by: Harry Wentland Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Fix bpc calculation for specific encodings

2021-11-03T16:32:34Z

[Why] 1. YCbCr 4:2:2 8bpc/10bpc modes are blocked for HDMI by policy 2. A YCbCr 4:2:0 calculation error blocked some 4:2:0 timing modes [How] YCbCr 4:2:2 8bpc/10bpc modes are allowed for HDMI Fix YCbCr 4:2:0 calculation error Acked-by: Aurabindo Pillai Signed-off-by: Bing Guo Reviewed-by: Chris Park Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: move FPU associated DCN301 code to DML folder

2021-10-28T18:26:50Z

[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN301 to DML, where all FPU code should locate. Cc: Christian König Cc: Harry Wentland Cc: Rodrigo Siqueira Tested-by: Zhan Liu Tested-by: Daniel Wheeler Signed-off-by: Qingqing Zhuo Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: move FPU associated DSC code to DML folder

2021-10-28T18:26:14Z

[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König Cc: Hersen Wu Cc: Anson Jacob Cc: Harry Wentland Reviewed-by: Rodrigo Siqueira Acked-by: Agustin Gutierrez Tested-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Qingqing Zhuo Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1

2021-10-19T21:19:06Z

[Why] Prefetch BW calculated is lower than the DML reference because of a porting error that's excluding cursor and row bandwidth from the pixel data bandwidth. [How] Change the dml_max4 to dml_max3 and include cursor and row bandwidth in the same calculation as the rest of the pixel data during vactive. Reviewed-by: Dmytro Laktyushkin Acked-by: Agustin Gutierrez Sanchez Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Re-arrange FPU code structure for dcn2x

2021-10-06T19:49:24Z

[Why] Current FPU code for DCN2x is located under dml/dcn2x. This is not aligned with DC's general source tree structure. [How] Move FPU code for DCN2x to dml/dcn20. Reviewed-by: Rodrigo Siqueira Acked-by: Solomon Chiu Signed-off-by: Qingqing Zhuo Signed-off-by: Alex Deucher

drm/amd/display: add cyan_skillfish display support

2021-10-04T19:22:57Z

[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu Signed-off-by: Zhan Liu Reviewed-by: Charlene Liu Acked-by: Jun Lei Acked-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/display: Reduce stack size for dml21_ModeSupportAndSystemConfigurationFull

2021-09-23T19:17:30Z

[Why & How] With Werror enabled in the kernel we were failing the clang build since dml21_ModeSupportAndSystemConfigurationFull's stack frame is 1064 when building with clang, and exceeding the default 1024 stack frame limit. The culprit seems to be the Pipe struct, so pull the relevant block out into its own sub-function. Signed-off-by: Harry Wentland Acked-by: Arnd Bergmann Reviewed-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Fix rest of pass-by-value structs in DML

2021-09-23T19:17:30Z

Passing structs adds a lot of overhead. We don't ever want to pass anything bigger than primitives by value. This patch fixes these Coverity IDs: Addresses-Coverity-ID: 1424031: ("Big parameter passed by value") Addresses-Coverity-ID: 1424055: ("Big parameter passed by value") Addresses-Coverity-ID: 1424072: ("Big parameter passed by value") Addresses-Coverity-ID: 1423779: ("Big parameter passed by value") Signed-off-by: Harry Wentland Cc: Nick Desaulniers Cc: Linus Torvalds Cc: amd-gfx@lists.freedesktop.org Cc: Linux Kernel Mailing List Cc: Arnd Bergmann Cc: Leo Li Cc: Alex Deucher Cc: Christian König Cc: Xinhui Pan Cc: Nathan Chancellor Cc: Guenter Roeck Cc: llvm@lists.linux.dev Acked-by: Christian König Build-tested-by: Nathan Chancellor Reviewed-by: Leo Li Signed-off-by: Alex Deucher