kernel.git/drivers/gpu/drm/amd/display/dc/dml, branch linux-5.11.y

drm/amd/display: Fix UBSAN: shift-out-of-bounds warning

2021-05-12T06:37:27Z

[ Upstream commit 54718747a6e1037317a8b3610c3be40621b2b75e ] [Why] On NAVI14 CONFIG_UBSAN reported shift-out-of-bounds at display_rq_dlg_calc_20v2.c:304:38 rq_param->misc.rq_c.blk256_height is 0 when chroma(*_c) is invalid. dml_log2 returns -1023 for log2(0), although log2(0) is undefined. Which ended up as: rq_param->dlg.rq_c.swath_height = 1 << -1023 [How] Fix applied on all dml versions. 1. Ensure dml_log2 is only called if the argument is greater than 0. 2. Subtract req128_l/req128_c from log2_swath_height_l/log2_swath_height_c only when it is greater than 0. Tested-by: Daniel Wheeler Signed-off-by: Anson Jacob Reviewed-by: Dmytro Laktyushkin Reviewed-by: Jun Lei Acked-by: Solomon Chiu Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: fix dml prefetch validation

2021-05-12T06:37:23Z

[ Upstream commit 8ee0fea4baf90e43efe2275de208a7809f9985bc ] Incorrect variable used, missing initialization during validation. Tested-by: Daniel Wheeler Signed-off-by: Dmytro Laktyushkin Reviewed-by: Eric Bernstein Acked-by: Solomon Chiu Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

Revert "drm/amd/display: Fixed Intermittent blue screen on OLED panel"

2021-01-14T05:23:01Z

commit a861736dae64 ("drm/amd/display: Fixed Intermittent blue screen on OLED panel") causes power regression for many users. It seems that this change causes the MCLK to get forced high; this creates a regression for many users since their devices were not able to drop to a low state after this change. For this reason, this reverts commit a861736dae644a0d7abbca0c638ae6aad28feeb8. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1407 Cc: Aurabindo Pillai Cc: Alex Deucher Cc: Harry Wentland Cc: Naveed Ashfaq Cc: Hersen Wu Cc: Roman Li Acked-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amdgpu/display: drop DCN support for aarch64

2021-01-06T21:24:10Z

From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon Reported-by: Ard Biesheuvel Signed-off-by: Alex Deucher

drm/amd/display: remove unused dml variables

2020-11-16T17:18:55Z

Signed-off-by: Dmytro Laktyushkin Acked-by: Bindu Ramamurthy Signed-off-by: Alex Deucher

drm/amd/display: correct dml dsc bpc assignment

2020-11-10T19:25:09Z

Signed-off-by: Dmytro Laktyushkin Acked-by: Bindu Ramamurthy Signed-off-by: Alex Deucher

drm/amd/display: Add fallback to prefetch mode 1 if 0 fails

2020-11-10T19:24:39Z

[Why] In some cases, prefetch mode 0 is unsupported but prefetch 1 is supported. Due to previous change always forcing prefetch mode to 0, we are failing bandwidth validation in cases where we should not. [How] By default try prefetch mode 0 but in the case validation fails, attempt to do prefetch mode 1 to see if it is supported. Signed-off-by: Isabel Zhang Acked-by: Bindu Ramamurthy Signed-off-by: Alex Deucher

drm/amdgpu/display: FP fixes for DCN3.x (v4)

2020-11-04T22:11:43Z

Add proper FP_START/END handling and adjust Makefiles per previous asics. v2: fix up harder. v3: fix clkmgr Makefile for dcn30 v4: fix old gcc handling is only required for x86 Build-tested-by: Nathan Chancellor Reviewed-by: Harry Wentland (v1) Reviewed-by: Nicholas Kazlauskas (v1) Signed-off-by: Alex Deucher

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04T22:11:37Z

Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov (v1) Signed-off-by: Alex Deucher

drm/amd/display: Revert HUBP blank behaviour for now

2020-11-02T20:31:57Z

[Why] Commit "Blank HUBP during pixel data blank for DCN30 v2" modifies HW behaviour during blank, which might have OS dependencies. We need to assess the impact on amdgpu_dm and only re-enable HUBP blanking when all necessary changes are understood. [How] - revert functional changes - leave architectural changes intact Signed-off-by: Joshua Aberback Reviewed-by: Jun Lei Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher