kernel.git/drivers/gpu/drm/amd/display/dc/dml2, branch linux-6.17.y

drm/amd/display/dml2: Guard dml21_map_dc_state_into_dml_display_cfg with DC_FP_START

2025-11-13T20:37:24Z

[ Upstream commit c97a7dccb3ed680031011cfc1457506e6de49c9a ] dml21_map_dc_state_into_dml_display_cfg calls (the call is usually inlined by the compiler) populate_dml21_surface_config_from_plane_state and populate_dml21_plane_config_from_plane_state which may use FPU. In a x86-64 build: $ objdump --disassemble=dml21_map_dc_state_into_dml_display_cfg \ > drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.o | > grep %xmm -c 63 Thus it needs to be guarded with DC_FP_START. But we must note that the current code quality of the in-kernel FPU use in AMD dml2 is very much problematic: we are actually calling DC_FP_START in dml21_wrapper.c here, and this translation unit is built with CC_FLAGS_FPU. Strictly speaking this does not make any sense: with CC_FLAGS_FPU the compiler is allowed to generate FPU uses anywhere in the translated code, perhaps out of the DC_FP_START guard. This problematic pattern also occurs in at least dml2_wrapper.c, dcn35_fpu.c, and dcn351_fpu.c. Thus we really need a careful audit and refactor for the in-kernel FPU uses, and this patch is simply whacking a mole. However per the reporter, whacking this mole is enough to make a 9060XT "just work." Reported-by: Asiacn <710187964@qq.com> Closes: https://github.com/loongson-community/discussions/issues/102 Tested-by: Asiacn <710187964@qq.com> Signed-off-by: Xi Ruoyao Reviewed-by: Huacai Chen Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: fix dml ms order of operations

2025-11-13T20:37:23Z

[ Upstream commit 02a6c2e4b28ff31f7a904c196a99fb2efe81e2cf ] [why&how] small error in order of operations in immediateflipbytes calculation on dml ms side that can result in dml ms and mp mismatch immediateflip support for a given pipe and thus an invalid hw state, correct the order to align with mp. Reviewed-by: Leo Chen Signed-off-by: Ausef Yousof Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Increase minimum clock for TMDS 420 with pipe splitting

2025-11-13T20:37:09Z

[ Upstream commit 002a612023c8b105bd3829d81862dee04368d6de ] [Why] -Pipe splitting allows for clocks to be reduced, but when using TMDS 420, reduced clocks lead to missed clocks cycles on clock resyncing [How] -Impose a minimum clock when using TMDS 420 Reviewed-by: Chris Park Signed-off-by: Relja Vojvodic Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Refactor DML21 Initialization and Configuration

2025-06-30T15:58:50Z

[Why & How] - Consolidated the initialization of DML21 parameters into a single function `dml21_populate_dml_init_params` to streamline the process and improve code readability. - Updated the function signatures in the header files to reflect changes in parameter passing for DML context. - Removed redundant debug option handling and integrated it into the new configuration population function. - Adjusted the DML21 initialization logic in the wrapper to accommodate the new structure, ensuring compatibility with different DCN versions. - Enhanced the handling of clock parameters and bounding box configurations from various sources, including hardware defaults and software policies. - Improved the clarity of the code by renaming functions and variables for better understanding of their purposes. Reviewed-by: Austin Zheng Signed-off-by: Wenjing Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: DML21 Reintegration

2025-06-24T13:58:07Z

Update logging macros for detailed debugging Update structs to contain more detailed information Add HDMI 16 and 20 Gbps rates Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Removed unnecessary comment

2025-06-24T13:55:30Z

Reviewed-by: Sridevi Arvindekar Signed-off-by: Alvin Lee Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Include EQU Prefetch Bandwidth For Bandwidth Calculations

2025-06-24T13:55:22Z

[Why] Pixel data bandwidth required in mode programming (MP) ends up being higher than what was calculated in mode support (MS) even though the prefetch bandwidths calculated in MP are lower than the MS ones. MP used a different equ prefetch schedule than MS which lead a slight difference in parameters. This resulted in the pixel data bandwidth in MP to be higher than MS. [How] Rename the RequiredPrefetchBWOTO term so it can be applied generically. Update the value with the EQU bandwidth if the EQU schedule is used. Get the max prefetch bandwidth that MS calculated and use it as part of the calculations for required bandwidth. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: remove use_native_pstate_optimization

2025-06-18T16:19:20Z

[Why] In DML2 (not DML2.1), DCN35 and DCN351 have the default value for use_native_pstate_optimization set to true. The code path where this bit is false is not used. [How] Remove the bit and the corresponding code path when it is set to false. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aric Cyr Signed-off-by: Yan Li Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: apply two different methods to validate modes

2025-06-18T16:19:19Z

[Why] In DML2, the current method to determine a mode is supported involves checking the voltage levels sequentially from the lowest, until one is found that can support the mode. It causes cursor lag due to low performance. [How] We apply two methods for mode validation. 1) DC_VALIDATE_MODE_ONLY: only the maximum voltage level is checked to determine whether the mode is supported, which improves performance and eliminate cursor lag. 2) DC_VALIDATE_MODE_AND_STATE_INDEX: when the optimal voltage level is required, check the voltage level from the lowest until a suitable one is found found and returns its index. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aric Cyr Signed-off-by: Yan Li Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: Fix RMCM programming seq errors

2025-06-18T16:19:17Z

[WHY & HOW] Fix RMCM programming sequence errors and mapping issues to pass the RMCM test. Cc: Mario Limonciello Cc: Alex Deucher Reviewed-by: Dmytro Laktyushkin Signed-off-by: Yihan Zhu Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher