<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dcn10, branch linux-5.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.2.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.2.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2019-10-07T16:58:53Z</updated>
<entry>
<title>drm/amd/display: fix issue where 252-255 values are clipped</title>
<updated>2019-10-07T16:58:53Z</updated>
<author>
<name>Anthony Koo</name>
</author>
<published>2019-07-12T14:52:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=73de2baa5b3c54d6c457c78964615cac1408caf6'/>
<id>urn:sha1:73de2baa5b3c54d6c457c78964615cac1408caf6</id>
<content type='text'>
[ Upstream commit 1cbcfc975164f397b449efb17f59d81a703090db ]

[Why]
When endpoint is at the boundary of a region, such as at 2^0=1
we find that the last segment has a sharp slope and some points
are clipped at the top.

[How]
If end point is 1, which is exactly at the 2^0 region boundary, we
need to program an additional region beyond this point.

Signed-off-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: allocate 4 ddc engines for RV2</title>
<updated>2019-08-16T08:11:01Z</updated>
<author>
<name>Derek Lai</name>
</author>
<published>2019-07-02T09:50:41Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2961a5916cb43938690aa56393ca1a6f1069b318'/>
<id>urn:sha1:2961a5916cb43938690aa56393ca1a6f1069b318</id>
<content type='text'>
[ Upstream commit 67fd6c0d2de8e51e84ff3fa6e68bbd524f823e49 ]

[Why]
Driver will create 0, 1, and 2 ddc engines for RV2,
but some platforms used 0, 1, and 3.

[How]
Still allocate 4 ddc engines for RV2.

Signed-off-by: Derek Lai &lt;Derek.Lai@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: put back front end initialization sequence</title>
<updated>2019-08-16T08:11:01Z</updated>
<author>
<name>Eric Yang</name>
</author>
<published>2019-06-24T22:18:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5b4fb99c395076fd88bc038caa2dc91718b7292c'/>
<id>urn:sha1:5b4fb99c395076fd88bc038caa2dc91718b7292c</id>
<content type='text'>
[ Upstream commit feb7eb522e0a7a22c1e60d386bd3c3bfa1d5e4f7 ]

[Why]
Seamless boot optimization removed proper front end power off sequence.
In driver disable enable case, this causes driver to power gate hubp
and dpp while there is still memory fetching going on, this can cause
invalid memory requests to be generated which will hang data fabric.

[How]
Put back proper front end power off sequence

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Clock does not lower in Updateplanes</title>
<updated>2019-08-16T08:11:00Z</updated>
<author>
<name>Murton Liu</name>
</author>
<published>2019-06-10T21:55:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=98d0152c2da000d48d78458874abf259a80d0c4c'/>
<id>urn:sha1:98d0152c2da000d48d78458874abf259a80d0c4c</id>
<content type='text'>
[ Upstream commit 492d9ec244923420af96db6b69ad7d575859aa92 ]

[why]
We reset the optimized_required in atomic_plane_disable
flag immediately after it is set in atomic_plane_disconnect, causing us to
never have flag set during next flip in UpdatePlanes.

[how]
Optimize directly after each time plane is removed.

Signed-off-by: Murton Liu &lt;murton.liu@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix compilation error</title>
<updated>2019-07-31T05:24:39Z</updated>
<author>
<name>Hariprasad Kelam</name>
</author>
<published>2019-06-13T02:32:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=91bac7fe5eb15a814312b0b532df193e51b09d01'/>
<id>urn:sha1:91bac7fe5eb15a814312b0b532df193e51b09d01</id>
<content type='text'>
[ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ]

this patch fixes below compilation error

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
function ‘dcn10_apply_ctx_for_surface’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2378:3:
error: implicit declaration of function ‘udelay’
[-Werror=implicit-function-declaration]
   udelay(underflow_check_delay_us);

Signed-off-by: Hariprasad Kelam &lt;hariprasad.kelam@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm-next</title>
<updated>2019-05-03T00:31:07Z</updated>
<author>
<name>Dave Airlie</name>
</author>
<published>2019-05-03T00:00:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=422449238e9853458283beffed77562d4b40a2fa'/>
<id>urn:sha1:422449238e9853458283beffed77562d4b40a2fa</id>
<content type='text'>
- SR-IOV fixes
- Raven flickering fix
- Misc spelling fixes
- Vega20 power fixes
- Freesync improvements
- DC fixes

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Alex Deucher &lt;alexdeucher@gmail.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190502193020.3562-1-alexander.deucher@amd.com
</content>
</entry>
<entry>
<title>drm/amd/display: Add hubp_init entry to hubp vtable</title>
<updated>2019-04-29T19:59:06Z</updated>
<author>
<name>Charlene Liu</name>
</author>
<published>2019-04-11T01:43:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cc8d84132a833cc3be469c5d363da769bc69875e'/>
<id>urn:sha1:cc8d84132a833cc3be469c5d363da769bc69875e</id>
<content type='text'>
Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1.

In addition, future HW will need to access the HUBPREQ_DEBUG register
for hubp_init. Add it to the reg list.

Signed-off-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove deprecated pplib interface</title>
<updated>2019-04-29T19:59:00Z</updated>
<author>
<name>Eric Yang</name>
</author>
<published>2019-04-10T18:08:53Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a0867053408ec4623687f574d8931286c54d514f'/>
<id>urn:sha1:a0867053408ec4623687f574d8931286c54d514f</id>
<content type='text'>
[Why]
The new interface now replaces the old interface for all known
configurations.

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add power down display on boot flag</title>
<updated>2019-04-29T19:58:53Z</updated>
<author>
<name>Thomas Lim</name>
</author>
<published>2019-04-10T21:06:07Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=27eaa4927dc3be669ed70670241597ac73595caf'/>
<id>urn:sha1:27eaa4927dc3be669ed70670241597ac73595caf</id>
<content type='text'>
[Why]

Due to the generic introduction of seamless boot, the display is no
longer blanked upon boot. However, this causes corruption on some
systems that does not lock the memory in the non-secure boot case,
resulting in brief corruption on boot due to garbage being written into
the frame buffer.

[How]
Add a flag, read during DC init, to determine whether display should be
blanked on boot. Default to true.

Signed-off-by: Thomas Lim &lt;Thomas.Lim@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor watermark programming</title>
<updated>2019-04-29T19:58:45Z</updated>
<author>
<name>Yongqiang Sun</name>
</author>
<published>2019-03-29T18:36:57Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=91f287566d494a4b28135f51e4698593feedc886'/>
<id>urn:sha1:91f287566d494a4b28135f51e4698593feedc886</id>
<content type='text'>
* Replace certain register writes with register sets that overwrites the
  the entire register, instead of only a field within the register.
* Add program_watermarks() entry to hubbub vtable. Hook it up to
  existing functions that program watermarks.
* Add additional watermark registers.

Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
