<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dce110, branch linux-5.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.2.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.2.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2019-07-31T05:24:32Z</updated>
<entry>
<title>drm/amd/display: Fill prescale_params-&gt;scale for RGB565</title>
<updated>2019-07-31T05:24:32Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
</author>
<published>2019-04-16T14:30:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ffd65f196223456a16c2755b260d7eaff201bfce'/>
<id>urn:sha1:ffd65f196223456a16c2755b260d7eaff201bfce</id>
<content type='text'>
[ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ]

[Why]
An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565
formats on DCE since the prescale_params-&gt;scale wasn't being filled.

Found by a dmesg-fail when running the
igt@kms_plane@pixel-format-pipe-a-planes test on Baffin.

[How]
Fill in the scale parameter.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add fast_validate parameter</title>
<updated>2019-04-15T05:22:11Z</updated>
<author>
<name>Joshua Aberback</name>
</author>
<published>2019-04-01T19:18:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=afcd526b1ba9dbc5707f9bd8d2d032ae62e337dc'/>
<id>urn:sha1:afcd526b1ba9dbc5707f9bd8d2d032ae62e337dc</id>
<content type='text'>
Add a fast_validate parameter in dc_validate_global_state for future use

Signed-off-by: Joshua Aberback &lt;joshua.aberback@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: expand plane caps to include fp16 and scaling capability</title>
<updated>2019-04-15T05:19:54Z</updated>
<author>
<name>Jun Lei</name>
</author>
<published>2019-03-26T21:32:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ea36ad34c5b2d6d2e079efc20fb0784e63dad438'/>
<id>urn:sha1:ea36ad34c5b2d6d2e079efc20fb0784e63dad438</id>
<content type='text'>
[why]
there are some scaling capabilities such as fp16 which are known to be unsupported
on a given ASIC.  exposing these static capabilities allows much simpler implementation
for OS interfaces which require to report such static capabilities to reduce the
number of dynamic validation calls

[how]
refactor the existing plane caps to be more extensible, and add fp16 and scaling
capabilities

Signed-off-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet Lakha@amd.com&gt;
Acked-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix clk_mgr naming</title>
<updated>2019-04-10T18:53:27Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
</author>
<published>2019-03-20T21:10:41Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=0de34efc7b5f1f34676dcdd7ed8bb8a20038724d'/>
<id>urn:sha1:0de34efc7b5f1f34676dcdd7ed8bb8a20038724d</id>
<content type='text'>
clk_mgr is called dccg in dc_state, this change fixes that

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Eric Bernstein &lt;Eric.Bernstein@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix multi-thread writing to 1 state</title>
<updated>2019-04-03T16:57:07Z</updated>
<author>
<name>Aidan Wood</name>
</author>
<published>2019-02-22T18:37:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=813d20dccf93f84f4c16236f7c037dc34db48f10'/>
<id>urn:sha1:813d20dccf93f84f4c16236f7c037dc34db48f10</id>
<content type='text'>
[Why]
Multiple threads were writing back to one global VBA in DC resulting
in multiple threads overwriting eachother's data

[How]
Add an instance of DML (which contains VBA) to each context and
change all calls that used dc-&gt;dml to use context-&gt;dml. Created a
seperate copy constructor for linux in a case where there is no
access to DC.

Signed-off-by: Aidan Wood &lt;Aidan.Wood@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: use dc_is_virtual instead of ENUM</title>
<updated>2019-03-28T03:42:51Z</updated>
<author>
<name>Eric Bernstein</name>
</author>
<published>2019-02-28T19:45:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=248cbed60db05f39913707c1ad74999730487fd6'/>
<id>urn:sha1:248cbed60db05f39913707c1ad74999730487fd6</id>
<content type='text'>
Signed-off-by: Eric Bernstein &lt;eric.bernstein@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Nevenko Stupar &lt;Nevenko.Stupar@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add missing opp programming for odm</title>
<updated>2019-03-21T04:39:48Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
</author>
<published>2019-03-08T22:09:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=661a8cd9516b182c80fff1b2fdfb1b1e42e212d1'/>
<id>urn:sha1:661a8cd9516b182c80fff1b2fdfb1b1e42e212d1</id>
<content type='text'>
A number of places opp programming was missing for odm second pipe.
This change fixes the oversight.

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DP audio regression</title>
<updated>2019-03-21T04:39:48Z</updated>
<author>
<name>Wesley Chalmers</name>
</author>
<published>2019-03-01T19:28:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fe6119fb0361521ba4df8887c1791df9c08296f1'/>
<id>urn:sha1:fe6119fb0361521ba4df8887c1791df9c08296f1</id>
<content type='text'>
Audio was unmuted for HDMI only, need to do so for DP as well.

Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Reviewed-by: Chris Park &lt;Chris.Park@amd.com&gt;
Reviewed-by: Eric Bernstein &lt;Eric.Bernstein@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix DP 422 VID_M half the rate issue.</title>
<updated>2019-03-21T04:39:48Z</updated>
<author>
<name>Charlene Liu</name>
</author>
<published>2019-03-01T16:12:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7fe538a4d64135d8f8e4aca8d0aedf266958025c'/>
<id>urn:sha1:7fe538a4d64135d8f8e4aca8d0aedf266958025c</id>
<content type='text'>
[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as  YCbCr444.

Signed-off-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Reviewed-by: Nikola Cornij &lt;Nikola.Cornij@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix setting DP_VID_N_MUL</title>
<updated>2019-03-21T04:39:48Z</updated>
<author>
<name>Eric Bernstein</name>
</author>
<published>2018-08-17T21:57:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ae5041f3a03134a4cd5fc1c41e082c0e5d290392'/>
<id>urn:sha1:ae5041f3a03134a4cd5fc1c41e082c0e5d290392</id>
<content type='text'>
[Why]
Need to set VID_N_MUL for 4:2:0 cases

[How]
Move setting to enc1_stream_encoder_dp_unblank and
ensure it is also set for non-4:2:0 cases.

Signed-off-by: Eric Bernstein &lt;eric.bernstein@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
