<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/dc.h, branch linux-6.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.14.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2025-04-20T08:22:37Z</updated>
<entry>
<title>drm/amd/display: add workaround flag to link to force FFE preset</title>
<updated>2025-04-20T08:22:37Z</updated>
<author>
<name>Brendan Tam</name>
</author>
<published>2025-01-23T16:25:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1af864e838b2c4e5ba23a71986eb1fc51f2b9d5b'/>
<id>urn:sha1:1af864e838b2c4e5ba23a71986eb1fc51f2b9d5b</id>
<content type='text'>
[ Upstream commit 51d1b338541dea83fec8e6f95d3e46fa469a73a8 ]

[Why]
There have been instances of some monitors being unable to link train on
their reported link speed using their selected FFE preset. If a different
FFE preset is found that has a higher rate of success during link training
this workaround can be used to force its FFE preset.

[How]
A new link workaround flag is made called force_dp_ffe_preset. The flag is
checked in override_training_settings and will set lt_settings-&gt;ffe_preset
which is null if the flag is not set. The flag is then set in
override_lane_settings.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Brendan Tam &lt;Brendan.Tam@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: 3.2.316</title>
<updated>2025-01-10T17:12:47Z</updated>
<author>
<name>Ryan Seto</name>
</author>
<published>2025-01-06T16:44:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=812a33a65d00e3d813f5ed2c9923569acd0b445c'/>
<id>urn:sha1:812a33a65d00e3d813f5ed2c9923569acd0b445c</id>
<content type='text'>
This version brings along following fixes:
- Add some feature for secure display
- Add replay desync error count tracking and reset
- Update chip_cap defines and usage
- Remove unnecessary eDP power down
- Fix some stuttering/corruption issue on PSR panel
- Cleanup and refactoring DML2.1

Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Reviewed-by: Martin Leung &lt;martin.leung@amd.com&gt;
Signed-off-by: Ryan Seto &lt;ryanseto@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Promote DC to 3.2.315</title>
<updated>2025-01-06T19:44:28Z</updated>
<author>
<name>Martin Leung</name>
</author>
<published>2024-12-16T14:08:04Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=da968c3ce459442e83b021d73417b9402c8b14c5'/>
<id>urn:sha1:da968c3ce459442e83b021d73417b9402c8b14c5</id>
<content type='text'>
This version brings along the following:
- Add Interface to Dump DSC Caps from dm
- Add DP required HBlank size calc to link interface
- Add 6bpc RGB case for dcn32 output bpp calculations
- Add VC for VESA Aux Backlight Control
- Add support for setting multiple CRC windows in dc
- Clean up SPL code and outdated interfaces in dcn401_clk_mgr
- Disable replay and psr while VRR is enabled
- Fix PSR-SU not support but still call the  amdgpu_dm_psr_enable
- Implement Replay Low Hz Visual Confirm
- Extend dc_stream_get_crc to support 2nd crc engine
- Update power gating logic for DCN35 hw

Reviewed-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Martin Leung &lt;Martin.Leung@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add VC for VESA Aux Backlight Control</title>
<updated>2025-01-06T19:44:28Z</updated>
<author>
<name>Iswara Nagulendran</name>
</author>
<published>2024-12-11T22:19:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d566fc42c0d33fea79bd8896ae6e77df67ae1ac8'/>
<id>urn:sha1:d566fc42c0d33fea79bd8896ae6e77df67ae1ac8</id>
<content type='text'>
[WHY]
There is no way to distinguish
the static backlight control type
being used and the VABC support
without the use of a debugger or
reading DPCD registers.

[HOW]
Add Visual Confirm support
for VESA Aux-based Backlight Control.

Reviewed-by: Harry Vanzylldejong &lt;harry.vanzylldejong@amd.com&gt;
Signed-off-by: Iswara Nagulendran &lt;Iswara.Nagulendran@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update dc_tiling_info union to structure</title>
<updated>2025-01-06T19:44:27Z</updated>
<author>
<name>Karthi Kandasamy</name>
</author>
<published>2024-11-20T12:30:11Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=080950cbdd8309110eab93b76f0caf53be0d5120'/>
<id>urn:sha1:080950cbdd8309110eab93b76f0caf53be0d5120</id>
<content type='text'>
[WHY]
The `dc_tiling_info` union previously did not have a field to
specify the active GFX format, assuming only one format would
be used per DCN version. from DCN4+, support for switching
between different GFX formats is introduced, requiring a way
to track which format is currently in use.

[HOW]
Updated the `dc_tiling_info` union to include a new field that
explicitly indicates the currently used GFX format.
This allows the system to determine the active GFX format
and take the correct programming path accordingly.

[Description]
The union `dc_tiling_info` has been updated to support multiple
GFX formats by adding a new field for identifying the active format.
This update ensures that the correct programming path is followed
based on the selected format. All references to `dc_tiling_info`
in the codebase have been updated to reflect the new structure.

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Karthi Kandasamy &lt;karthi.kandasamy@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: have pretrain for dpia</title>
<updated>2025-01-06T19:44:27Z</updated>
<author>
<name>Peichen Huang</name>
</author>
<published>2024-12-04T07:20:10Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=44063dbcdbd8abf172b8cc30e18d7e2948e9d699'/>
<id>urn:sha1:44063dbcdbd8abf172b8cc30e18d7e2948e9d699</id>
<content type='text'>
[WHY]
We like to have pretrain for dpia link so that dp and dp tunneling
have aligned behavior. The Main difficult for dpia pretrain is that
encoder can not get corresponded dpia port when link detection
in current implementation.

[HOW]
1. create enable/disable dpia output functions for dcn35 encoder
and have dpia_id and other necessary info as inputs.
2. dcn35 dpia use the new functions to enable/disable output.
3. have a option to enable/disable the change.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DP required HBlank size calc to link interface</title>
<updated>2025-01-06T19:44:26Z</updated>
<author>
<name>George Shen</name>
</author>
<published>2024-12-09T15:29:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3ed56d9e8f483994bc5697b59057ab2adf4750ed'/>
<id>urn:sha1:3ed56d9e8f483994bc5697b59057ab2adf4750ed</id>
<content type='text'>
[Why]
Some features, such as HBlank expansion/reduction, needs to know how
much HBlank is required to support basic audio.

[How]
Add interface to link to calculate required HBlank size for a given
link + timing combination to support basic audio (i.e. 2-channel 48KHz).

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Parse RECEIVE_PORT0_CAP capabilities from DPCD</title>
<updated>2025-01-06T19:44:26Z</updated>
<author>
<name>George Shen</name>
</author>
<published>2024-12-04T23:10:18Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e79cba63de318faa80804701563e58d880c2c492'/>
<id>urn:sha1:e79cba63de318faa80804701563e58d880c2c492</id>
<content type='text'>
[Why]
DPCD register RECEIVE_PORT0_CAP contains HBlank expansion/reduction
capabilities of a DP device. These capabilities are required to enable
HBlank expansion/reduction logic.

[How]
Read raw RECEIVE_PORT0_CAP register values and store parsed fields.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Cleanup outdated interfaces in dcn401_clk_mgr</title>
<updated>2025-01-06T19:44:26Z</updated>
<author>
<name>Dillon Varone</name>
</author>
<published>2024-12-09T17:21:51Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f0aece43ee75b48cc6846a66973565ddcce59c91'/>
<id>urn:sha1:f0aece43ee75b48cc6846a66973565ddcce59c91</id>
<content type='text'>
[WHY&amp;HOW]
- Remove legacy update clocks sequence
- FCLK P-State allow message is not required

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: increase MAX_SURFACES to the value supported by hw</title>
<updated>2024-12-19T22:39:05Z</updated>
<author>
<name>Melissa Wen</name>
</author>
<published>2024-12-17T20:45:04Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b8d6daffc871a42026c3c20bff7b8fa0302298c1'/>
<id>urn:sha1:b8d6daffc871a42026c3c20bff7b8fa0302298c1</id>
<content type='text'>
As the hw supports up to 4 surfaces, increase the maximum number of
surfaces to prevent the DC error when trying to use more than three
planes.

[drm:dc_state_add_plane [amdgpu]] *ERROR* Surface: can not attach plane_state 000000003e2cb82c! Maximum is: 3

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3693
Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
